158 lines
3.7 KiB
C
158 lines
3.7 KiB
C
/*
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* plat smp support for CSR Marco dual-core SMP SoCs
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*
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* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/page.h>
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#include <asm/mach/map.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <mach/map.h>
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#include "common.h"
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static void __iomem *scu_base;
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static void __iomem *rsc_base;
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static DEFINE_SPINLOCK(boot_lock);
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static struct map_desc scu_io_desc __initdata = {
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.length = SZ_4K,
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.type = MT_DEVICE,
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};
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void __init sirfsoc_map_scu(void)
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{
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unsigned long base;
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/* Get SCU base */
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
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scu_io_desc.virtual = SIRFSOC_VA(base);
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scu_io_desc.pfn = __phys_to_pfn(base);
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iotable_init(&scu_io_desc, 1);
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scu_base = (void __iomem *)SIRFSOC_VA(base);
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}
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static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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pen_release = -1;
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smp_wmb();
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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static struct of_device_id rsc_ids[] = {
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{ .compatible = "sirf,marco-rsc" },
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{},
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};
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static int __cpuinit sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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struct device_node *np;
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np = of_find_matching_node(NULL, rsc_ids);
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if (!np)
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return -ENODEV;
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rsc_base = of_iomap(np, 0);
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if (!rsc_base)
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return -ENOMEM;
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/*
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* write the address of secondary startup into the sram register
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* at offset 0x2C, then write the magic number 0x3CAF5D62 to the
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* RSC register at offset 0x28, which is what boot rom code is
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* waiting for. This would wake up the secondary core from WFE
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*/
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#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2C
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__raw_writel(virt_to_phys(sirfsoc_secondary_startup),
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rsc_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
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#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x28
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__raw_writel(0x3CAF5D62,
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rsc_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
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/* make sure write buffer is drained */
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mb();
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*
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* Note that "pen_release" is the hardware CPU ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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pen_release = cpu_logical_map(cpu);
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__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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/*
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* Send the secondary CPU SEV, thereby causing the boot monitor to read
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* the JUMPADDR and WAKEMAGIC, and branch to the address found there.
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*/
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dsb_sev();
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus)
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{
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scu_enable(scu_base);
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}
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struct smp_operations sirfsoc_smp_ops __initdata = {
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.smp_prepare_cpus = sirfsoc_smp_prepare_cpus,
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.smp_secondary_init = sirfsoc_secondary_init,
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.smp_boot_secondary = sirfsoc_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = sirfsoc_cpu_die,
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#endif
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};
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