164 lines
3.9 KiB
C
164 lines
3.9 KiB
C
/*
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* Broadcom specific AMBA
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* PCI Core
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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#include <linux/bcma/bcma.h>
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/**************************************************
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* R/W ops.
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**************************************************/
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static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
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{
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pcicore_write32(pc, 0x130, address);
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pcicore_read32(pc, 0x130);
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return pcicore_read32(pc, 0x134);
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}
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#if 0
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static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
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{
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pcicore_write32(pc, 0x130, address);
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pcicore_read32(pc, 0x130);
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pcicore_write32(pc, 0x134, data);
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}
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#endif
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static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
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{
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const u16 mdio_control = 0x128;
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const u16 mdio_data = 0x12C;
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u32 v;
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int i;
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v = (1 << 30); /* Start of Transaction */
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v |= (1 << 28); /* Write Transaction */
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v |= (1 << 17); /* Turnaround */
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v |= (0x1F << 18);
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v |= (phy << 4);
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pcicore_write32(pc, mdio_data, v);
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udelay(10);
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for (i = 0; i < 200; i++) {
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v = pcicore_read32(pc, mdio_control);
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if (v & 0x100 /* Trans complete */)
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break;
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msleep(1);
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}
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}
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static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
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{
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const u16 mdio_control = 0x128;
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const u16 mdio_data = 0x12C;
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int max_retries = 10;
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u16 ret = 0;
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u32 v;
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int i;
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v = 0x80; /* Enable Preamble Sequence */
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v |= 0x2; /* MDIO Clock Divisor */
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pcicore_write32(pc, mdio_control, v);
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if (pc->core->id.rev >= 10) {
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max_retries = 200;
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bcma_pcie_mdio_set_phy(pc, device);
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}
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v = (1 << 30); /* Start of Transaction */
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v |= (1 << 29); /* Read Transaction */
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v |= (1 << 17); /* Turnaround */
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if (pc->core->id.rev < 10)
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v |= (u32)device << 22;
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v |= (u32)address << 18;
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pcicore_write32(pc, mdio_data, v);
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/* Wait for the device to complete the transaction */
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udelay(10);
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for (i = 0; i < max_retries; i++) {
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v = pcicore_read32(pc, mdio_control);
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if (v & 0x100 /* Trans complete */) {
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udelay(10);
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ret = pcicore_read32(pc, mdio_data);
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break;
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}
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msleep(1);
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}
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pcicore_write32(pc, mdio_control, 0);
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return ret;
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}
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static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
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u8 address, u16 data)
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{
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const u16 mdio_control = 0x128;
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const u16 mdio_data = 0x12C;
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int max_retries = 10;
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u32 v;
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int i;
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v = 0x80; /* Enable Preamble Sequence */
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v |= 0x2; /* MDIO Clock Divisor */
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pcicore_write32(pc, mdio_control, v);
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if (pc->core->id.rev >= 10) {
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max_retries = 200;
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bcma_pcie_mdio_set_phy(pc, device);
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}
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v = (1 << 30); /* Start of Transaction */
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v |= (1 << 28); /* Write Transaction */
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v |= (1 << 17); /* Turnaround */
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if (pc->core->id.rev < 10)
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v |= (u32)device << 22;
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v |= (u32)address << 18;
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v |= data;
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pcicore_write32(pc, mdio_data, v);
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/* Wait for the device to complete the transaction */
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udelay(10);
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for (i = 0; i < max_retries; i++) {
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v = pcicore_read32(pc, mdio_control);
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if (v & 0x100 /* Trans complete */)
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break;
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msleep(1);
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}
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pcicore_write32(pc, mdio_control, 0);
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}
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/**************************************************
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* Workarounds.
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**************************************************/
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static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
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{
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return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
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}
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static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
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{
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const u8 serdes_pll_device = 0x1D;
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const u8 serdes_rx_device = 0x1F;
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u16 tmp;
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bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
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bcma_pcicore_polarity_workaround(pc));
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tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
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if (tmp & 0x4000)
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bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
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}
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/**************************************************
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* Init.
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**************************************************/
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void bcma_core_pci_init(struct bcma_drv_pci *pc)
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{
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bcma_pcicore_serdes_workaround(pc);
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}
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