568 lines
14 KiB
C
568 lines
14 KiB
C
/*
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* Marvell 10G 88x3310 PHY driver
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*
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* Based upon the ID registers, this PHY appears to be a mixture of IPs
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* from two different companies.
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*
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* There appears to be several different data paths through the PHY which
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* are automatically managed by the PHY. The following has been determined
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* via observation and experimentation for a setup using single-lane Serdes:
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*
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* SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
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* 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
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* 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
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*
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* With XAUI, observation shows:
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*
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* XAUI PHYXS -- <appropriate PCS as above>
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*
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* and no switching of the host interface mode occurs.
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*
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* If both the fiber and copper ports are connected, the first to gain
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* link takes priority and the other port is completely locked out.
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*/
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#include <linux/ctype.h>
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#include <linux/hwmon.h>
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#include <linux/marvell_phy.h>
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#include <linux/phy.h>
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enum {
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MV_PCS_BASE_T = 0x0000,
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MV_PCS_BASE_R = 0x1000,
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MV_PCS_1000BASEX = 0x2000,
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MV_PCS_PAIRSWAP = 0x8182,
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MV_PCS_PAIRSWAP_MASK = 0x0003,
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MV_PCS_PAIRSWAP_AB = 0x0002,
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MV_PCS_PAIRSWAP_NONE = 0x0003,
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/* These registers appear at 0x800X and 0xa00X - the 0xa00X control
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* registers appear to set themselves to the 0x800X when AN is
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* restarted, but status registers appear readable from either.
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*/
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MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
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MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
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/* Vendor2 MMD registers */
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MV_V2_TEMP_CTRL = 0xf08a,
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MV_V2_TEMP_CTRL_MASK = 0xc000,
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MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
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MV_V2_TEMP_CTRL_DISABLE = 0xc000,
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MV_V2_TEMP = 0xf08c,
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MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
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};
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struct mv3310_priv {
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struct device *hwmon_dev;
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char *hwmon_name;
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};
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static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
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u16 mask, u16 bits)
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{
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int old, val, ret;
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old = phy_read_mmd(phydev, devad, reg);
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if (old < 0)
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return old;
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val = (old & ~mask) | (bits & mask);
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if (val == old)
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return 0;
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ret = phy_write_mmd(phydev, devad, reg, val);
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return ret < 0 ? ret : 1;
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}
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#ifdef CONFIG_HWMON
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static umode_t mv3310_hwmon_is_visible(const void *data,
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enum hwmon_sensor_types type,
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u32 attr, int channel)
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{
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if (type == hwmon_chip && attr == hwmon_chip_update_interval)
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return 0444;
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if (type == hwmon_temp && attr == hwmon_temp_input)
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return 0444;
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return 0;
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}
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static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
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u32 attr, int channel, long *value)
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{
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struct phy_device *phydev = dev_get_drvdata(dev);
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int temp;
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if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
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*value = MSEC_PER_SEC;
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return 0;
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}
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if (type == hwmon_temp && attr == hwmon_temp_input) {
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temp = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
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if (temp < 0)
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return temp;
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*value = ((temp & 0xff) - 75) * 1000;
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return 0;
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}
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return -EOPNOTSUPP;
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}
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static const struct hwmon_ops mv3310_hwmon_ops = {
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.is_visible = mv3310_hwmon_is_visible,
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.read = mv3310_hwmon_read,
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};
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static u32 mv3310_hwmon_chip_config[] = {
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HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
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0,
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};
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static const struct hwmon_channel_info mv3310_hwmon_chip = {
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.type = hwmon_chip,
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.config = mv3310_hwmon_chip_config,
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};
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static u32 mv3310_hwmon_temp_config[] = {
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HWMON_T_INPUT,
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0,
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};
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static const struct hwmon_channel_info mv3310_hwmon_temp = {
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.type = hwmon_temp,
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.config = mv3310_hwmon_temp_config,
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};
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static const struct hwmon_channel_info *mv3310_hwmon_info[] = {
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&mv3310_hwmon_chip,
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&mv3310_hwmon_temp,
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NULL,
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};
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static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
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.ops = &mv3310_hwmon_ops,
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.info = mv3310_hwmon_info,
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};
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static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
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{
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u16 val;
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int ret;
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
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MV_V2_TEMP_UNKNOWN);
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if (ret < 0)
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return ret;
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val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
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ret = mv3310_modify(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
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MV_V2_TEMP_CTRL_MASK, val);
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return ret < 0 ? ret : 0;
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}
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static void mv3310_hwmon_disable(void *data)
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{
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struct phy_device *phydev = data;
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mv3310_hwmon_config(phydev, false);
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}
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static int mv3310_hwmon_probe(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
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int i, j, ret;
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priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
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if (!priv->hwmon_name)
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return -ENODEV;
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for (i = j = 0; priv->hwmon_name[i]; i++) {
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if (isalnum(priv->hwmon_name[i])) {
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if (i != j)
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priv->hwmon_name[j] = priv->hwmon_name[i];
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j++;
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}
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}
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priv->hwmon_name[j] = '\0';
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ret = mv3310_hwmon_config(phydev, true);
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if (ret)
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return ret;
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ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev);
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if (ret)
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return ret;
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priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
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priv->hwmon_name, phydev,
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&mv3310_hwmon_chip_info, NULL);
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return PTR_ERR_OR_ZERO(priv->hwmon_dev);
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}
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#else
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static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
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{
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return 0;
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}
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static int mv3310_hwmon_probe(struct phy_device *phydev)
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{
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return 0;
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}
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#endif
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static int mv3310_probe(struct phy_device *phydev)
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{
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struct mv3310_priv *priv;
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u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
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int ret;
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if (!phydev->is_c45 ||
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(phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
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return -ENODEV;
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priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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dev_set_drvdata(&phydev->mdio.dev, priv);
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ret = mv3310_hwmon_probe(phydev);
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if (ret)
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return ret;
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return 0;
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}
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static int mv3310_suspend(struct phy_device *phydev)
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{
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return 0;
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}
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static int mv3310_resume(struct phy_device *phydev)
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{
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return mv3310_hwmon_config(phydev, true);
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}
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static int mv3310_config_init(struct phy_device *phydev)
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{
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__ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
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u32 mask;
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int val;
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/* Check that the PHY interface type is compatible */
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if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
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phydev->interface != PHY_INTERFACE_MODE_XAUI &&
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phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
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phydev->interface != PHY_INTERFACE_MODE_10GKR)
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return -ENODEV;
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__set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
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__set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
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if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) {
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
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if (val < 0)
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return val;
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if (val & MDIO_AN_STAT1_ABLE)
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__set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
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}
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val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
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if (val < 0)
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return val;
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/* Ethtool does not support the WAN mode bits */
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if (val & (MDIO_PMA_STAT2_10GBSR | MDIO_PMA_STAT2_10GBLR |
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MDIO_PMA_STAT2_10GBER | MDIO_PMA_STAT2_10GBLX4 |
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MDIO_PMA_STAT2_10GBSW | MDIO_PMA_STAT2_10GBLW |
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MDIO_PMA_STAT2_10GBEW))
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__set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
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if (val & MDIO_PMA_STAT2_10GBSR)
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__set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, supported);
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if (val & MDIO_PMA_STAT2_10GBLR)
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__set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, supported);
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if (val & MDIO_PMA_STAT2_10GBER)
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__set_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, supported);
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if (val & MDIO_PMA_STAT2_EXTABLE) {
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val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
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if (val < 0)
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return val;
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if (val & (MDIO_PMA_EXTABLE_10GBT | MDIO_PMA_EXTABLE_1000BT |
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MDIO_PMA_EXTABLE_100BTX | MDIO_PMA_EXTABLE_10BT))
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__set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported);
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if (val & MDIO_PMA_EXTABLE_10GBLRM)
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__set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
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if (val & (MDIO_PMA_EXTABLE_10GBKX4 | MDIO_PMA_EXTABLE_10GBKR |
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MDIO_PMA_EXTABLE_1000BKX))
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__set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, supported);
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if (val & MDIO_PMA_EXTABLE_10GBLRM)
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__set_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
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supported);
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if (val & MDIO_PMA_EXTABLE_10GBT)
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__set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
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supported);
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if (val & MDIO_PMA_EXTABLE_10GBKX4)
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__set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
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supported);
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if (val & MDIO_PMA_EXTABLE_10GBKR)
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__set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
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supported);
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if (val & MDIO_PMA_EXTABLE_1000BT)
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__set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
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supported);
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if (val & MDIO_PMA_EXTABLE_1000BKX)
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__set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
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supported);
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if (val & MDIO_PMA_EXTABLE_100BTX) {
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__set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
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supported);
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__set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
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supported);
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}
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if (val & MDIO_PMA_EXTABLE_10BT) {
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__set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
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supported);
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__set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
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supported);
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}
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}
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if (!ethtool_convert_link_mode_to_legacy_u32(&mask, supported))
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dev_warn(&phydev->mdio.dev,
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"PHY supports (%*pb) more modes than phylib supports, some modes not supported.\n",
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__ETHTOOL_LINK_MODE_MASK_NBITS, supported);
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phydev->supported &= mask;
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phydev->advertising &= phydev->supported;
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return 0;
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}
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static int mv3310_config_aneg(struct phy_device *phydev)
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{
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bool changed = false;
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u32 advertising;
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int ret;
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/* We don't support manual MDI control */
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phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
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if (phydev->autoneg == AUTONEG_DISABLE) {
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ret = genphy_c45_pma_setup_forced(phydev);
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if (ret < 0)
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return ret;
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return genphy_c45_an_disable_aneg(phydev);
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}
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phydev->advertising &= phydev->supported;
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advertising = phydev->advertising;
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ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
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ADVERTISE_ALL | ADVERTISE_100BASE4 |
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ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
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ethtool_adv_to_mii_adv_t(advertising));
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
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ADVERTISE_1000FULL | ADVERTISE_1000HALF,
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ethtool_adv_to_mii_ctrl1000_t(advertising));
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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/* 10G control register */
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ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
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MDIO_AN_10GBT_CTRL_ADV10G,
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advertising & ADVERTISED_10000baseT_Full ?
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MDIO_AN_10GBT_CTRL_ADV10G : 0);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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if (changed)
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ret = genphy_c45_restart_aneg(phydev);
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return ret;
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}
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static int mv3310_aneg_done(struct phy_device *phydev)
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{
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int val;
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val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
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if (val < 0)
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return val;
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if (val & MDIO_STAT1_LSTATUS)
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return 1;
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return genphy_c45_aneg_done(phydev);
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}
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static void mv3310_update_interface(struct phy_device *phydev)
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{
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if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
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phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
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/* The PHY automatically switches its serdes interface (and
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* active PHYXS instance) between Cisco SGMII and 10GBase-KR
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* modes according to the speed. Florian suggests setting
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* phydev->interface to communicate this to the MAC. Only do
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* this if we are already in either SGMII or 10GBase-KR mode.
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*/
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if (phydev->speed == SPEED_10000)
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phydev->interface = PHY_INTERFACE_MODE_10GKR;
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else if (phydev->speed >= SPEED_10 &&
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phydev->speed < SPEED_10000)
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phydev->interface = PHY_INTERFACE_MODE_SGMII;
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}
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}
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/* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
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static int mv3310_read_10gbr_status(struct phy_device *phydev)
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{
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phydev->link = 1;
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phydev->speed = SPEED_10000;
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phydev->duplex = DUPLEX_FULL;
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mv3310_update_interface(phydev);
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return 0;
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}
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static int mv3310_read_status(struct phy_device *phydev)
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{
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u32 mmd_mask = phydev->c45_ids.devices_in_package;
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int val;
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/* The vendor devads do not report link status. Avoid the PHYXS
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* instance as there are three, and its status depends on the MAC
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* being appropriately configured for the negotiated speed.
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*/
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mmd_mask &= ~(BIT(MDIO_MMD_VEND1) | BIT(MDIO_MMD_VEND2) |
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BIT(MDIO_MMD_PHYXS));
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phydev->speed = SPEED_UNKNOWN;
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phydev->duplex = DUPLEX_UNKNOWN;
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phydev->lp_advertising = 0;
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phydev->link = 0;
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phydev->pause = 0;
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phydev->asym_pause = 0;
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phydev->mdix = 0;
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val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
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if (val < 0)
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return val;
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if (val & MDIO_STAT1_LSTATUS)
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return mv3310_read_10gbr_status(phydev);
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val = genphy_c45_read_link(phydev, mmd_mask);
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if (val < 0)
|
|
return val;
|
|
|
|
phydev->link = val > 0 ? 1 : 0;
|
|
|
|
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
|
|
if (val < 0)
|
|
return val;
|
|
|
|
if (val & MDIO_AN_STAT1_COMPLETE) {
|
|
val = genphy_c45_read_lpa(phydev);
|
|
if (val < 0)
|
|
return val;
|
|
|
|
/* Read the link partner's 1G advertisement */
|
|
val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
|
|
if (val < 0)
|
|
return val;
|
|
|
|
phydev->lp_advertising |= mii_stat1000_to_ethtool_lpa_t(val);
|
|
|
|
if (phydev->autoneg == AUTONEG_ENABLE)
|
|
phy_resolve_aneg_linkmode(phydev);
|
|
}
|
|
|
|
if (phydev->autoneg != AUTONEG_ENABLE) {
|
|
val = genphy_c45_read_pma(phydev);
|
|
if (val < 0)
|
|
return val;
|
|
}
|
|
|
|
if (phydev->speed == SPEED_10000) {
|
|
val = genphy_c45_read_mdix(phydev);
|
|
if (val < 0)
|
|
return val;
|
|
} else {
|
|
val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP);
|
|
if (val < 0)
|
|
return val;
|
|
|
|
switch (val & MV_PCS_PAIRSWAP_MASK) {
|
|
case MV_PCS_PAIRSWAP_AB:
|
|
phydev->mdix = ETH_TP_MDI_X;
|
|
break;
|
|
case MV_PCS_PAIRSWAP_NONE:
|
|
phydev->mdix = ETH_TP_MDI;
|
|
break;
|
|
default:
|
|
phydev->mdix = ETH_TP_MDI_INVALID;
|
|
break;
|
|
}
|
|
}
|
|
|
|
mv3310_update_interface(phydev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct phy_driver mv3310_drivers[] = {
|
|
{
|
|
.phy_id = 0x002b09aa,
|
|
.phy_id_mask = MARVELL_PHY_ID_MASK,
|
|
.name = "mv88x3310",
|
|
.features = SUPPORTED_10baseT_Full |
|
|
SUPPORTED_10baseT_Half |
|
|
SUPPORTED_100baseT_Full |
|
|
SUPPORTED_100baseT_Half |
|
|
SUPPORTED_1000baseT_Full |
|
|
SUPPORTED_Autoneg |
|
|
SUPPORTED_TP |
|
|
SUPPORTED_FIBRE |
|
|
SUPPORTED_10000baseT_Full |
|
|
SUPPORTED_Backplane,
|
|
.soft_reset = gen10g_no_soft_reset,
|
|
.config_init = mv3310_config_init,
|
|
.probe = mv3310_probe,
|
|
.suspend = mv3310_suspend,
|
|
.resume = mv3310_resume,
|
|
.config_aneg = mv3310_config_aneg,
|
|
.aneg_done = mv3310_aneg_done,
|
|
.read_status = mv3310_read_status,
|
|
},
|
|
};
|
|
|
|
module_phy_driver(mv3310_drivers);
|
|
|
|
static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
|
|
{ 0x002b09aa, MARVELL_PHY_ID_MASK },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
|
|
MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");
|
|
MODULE_LICENSE("GPL");
|