189 lines
4.9 KiB
C
189 lines
4.9 KiB
C
#ifndef _ASM_IA64_MMU_CONTEXT_H
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#define _ASM_IA64_MMU_CONTEXT_H
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/*
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* Copyright (C) 1998-2002 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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*/
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/*
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* Routines to manage the allocation of task context numbers. Task context numbers are
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* used to reduce or eliminate the need to perform TLB flushes due to context switches.
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* Context numbers are implemented using ia-64 region ids. Since the IA-64 TLB does not
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* consider the region number when performing a TLB lookup, we need to assign a unique
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* region id to each region in a process. We use the least significant three bits in a
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* region id for this purpose.
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*/
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#define IA64_REGION_ID_KERNEL 0 /* the kernel's region id (tlb.c depends on this being 0) */
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#define ia64_rid(ctx,addr) (((ctx) << 3) | (addr >> 61))
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# include <asm/page.h>
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# ifndef __ASSEMBLY__
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#include <linux/compiler.h>
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#include <linux/percpu.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <asm/processor.h>
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struct ia64_ctx {
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spinlock_t lock;
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unsigned int next; /* next context number to use */
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unsigned int limit; /* next >= limit => must call wrap_mmu_context() */
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unsigned int max_ctx; /* max. context value supported by all CPUs */
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};
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extern struct ia64_ctx ia64_ctx;
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DECLARE_PER_CPU(u8, ia64_need_tlb_flush);
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extern void wrap_mmu_context (struct mm_struct *mm);
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static inline void
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enter_lazy_tlb (struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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/*
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* When the context counter wraps around all TLBs need to be flushed because an old
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* context number might have been reused. This is signalled by the ia64_need_tlb_flush
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* per-CPU variable, which is checked in the routine below. Called by activate_mm().
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* <efocht@ess.nec.de>
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*/
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static inline void
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delayed_tlb_flush (void)
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{
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extern void local_flush_tlb_all (void);
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unsigned long flags;
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if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) {
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spin_lock_irqsave(&ia64_ctx.lock, flags);
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{
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if (__ia64_per_cpu_var(ia64_need_tlb_flush)) {
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local_flush_tlb_all();
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__ia64_per_cpu_var(ia64_need_tlb_flush) = 0;
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}
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}
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spin_unlock_irqrestore(&ia64_ctx.lock, flags);
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}
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}
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static inline nv_mm_context_t
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get_mmu_context (struct mm_struct *mm)
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{
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unsigned long flags;
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nv_mm_context_t context = mm->context;
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if (unlikely(!context)) {
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spin_lock_irqsave(&ia64_ctx.lock, flags);
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{
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/* re-check, now that we've got the lock: */
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context = mm->context;
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if (context == 0) {
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cpus_clear(mm->cpu_vm_mask);
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if (ia64_ctx.next >= ia64_ctx.limit)
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wrap_mmu_context(mm);
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mm->context = context = ia64_ctx.next++;
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}
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}
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spin_unlock_irqrestore(&ia64_ctx.lock, flags);
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}
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/*
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* Ensure we're not starting to use "context" before any old
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* uses of it are gone from our TLB.
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*/
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delayed_tlb_flush();
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return context;
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}
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/*
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* Initialize context number to some sane value. MM is guaranteed to be a brand-new
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* address-space, so no TLB flushing is needed, ever.
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*/
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static inline int
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init_new_context (struct task_struct *p, struct mm_struct *mm)
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{
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mm->context = 0;
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return 0;
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}
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static inline void
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destroy_context (struct mm_struct *mm)
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{
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/* Nothing to do. */
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}
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static inline void
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reload_context (nv_mm_context_t context)
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{
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unsigned long rid;
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unsigned long rid_incr = 0;
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unsigned long rr0, rr1, rr2, rr3, rr4, old_rr4;
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old_rr4 = ia64_get_rr(RGN_BASE(RGN_HPAGE));
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rid = context << 3; /* make space for encoding the region number */
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rid_incr = 1 << 8;
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/* encode the region id, preferred page size, and VHPT enable bit: */
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rr0 = (rid << 8) | (PAGE_SHIFT << 2) | 1;
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rr1 = rr0 + 1*rid_incr;
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rr2 = rr0 + 2*rid_incr;
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rr3 = rr0 + 3*rid_incr;
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rr4 = rr0 + 4*rid_incr;
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#ifdef CONFIG_HUGETLB_PAGE
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rr4 = (rr4 & (~(0xfcUL))) | (old_rr4 & 0xfc);
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# if RGN_HPAGE != 4
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# error "reload_context assumes RGN_HPAGE is 4"
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# endif
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#endif
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ia64_set_rr(0x0000000000000000UL, rr0);
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ia64_set_rr(0x2000000000000000UL, rr1);
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ia64_set_rr(0x4000000000000000UL, rr2);
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ia64_set_rr(0x6000000000000000UL, rr3);
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ia64_set_rr(0x8000000000000000UL, rr4);
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ia64_srlz_i(); /* srlz.i implies srlz.d */
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}
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/*
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* Must be called with preemption off
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*/
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static inline void
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activate_context (struct mm_struct *mm)
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{
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nv_mm_context_t context;
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do {
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context = get_mmu_context(mm);
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if (!cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
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cpu_set(smp_processor_id(), mm->cpu_vm_mask);
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reload_context(context);
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/* in the unlikely event of a TLB-flush by another thread, redo the load: */
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} while (unlikely(context != mm->context));
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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/*
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* Switch from address space PREV to address space NEXT.
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*/
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static inline void
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activate_mm (struct mm_struct *prev, struct mm_struct *next)
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{
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/*
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* We may get interrupts here, but that's OK because interrupt handlers cannot
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* touch user-space.
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*/
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ia64_set_kr(IA64_KR_PT_BASE, __pa(next->pgd));
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activate_context(next);
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}
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#define switch_mm(prev_mm,next_mm,next_task) activate_mm(prev_mm, next_mm)
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# endif /* ! __ASSEMBLY__ */
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#endif /* _ASM_IA64_MMU_CONTEXT_H */
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