334 lines
8.3 KiB
C
334 lines
8.3 KiB
C
#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/wait.h>
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#include "pci.h"
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/*
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* This interrupt-safe spinlock protects all accesses to PCI
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* configuration space.
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*/
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static DEFINE_SPINLOCK(pci_lock);
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/*
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* Wrappers for all PCI configuration access functions. They just check
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* alignment, do locking and call the low-level functions pointed to
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* by pci_dev->ops.
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*/
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#define PCI_byte_BAD 0
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#define PCI_word_BAD (pos & 1)
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#define PCI_dword_BAD (pos & 3)
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#define PCI_OP_READ(size,type,len) \
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int pci_bus_read_config_##size \
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(struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
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{ \
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int res; \
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unsigned long flags; \
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u32 data = 0; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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spin_lock_irqsave(&pci_lock, flags); \
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res = bus->ops->read(bus, devfn, pos, len, &data); \
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*value = (type)data; \
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spin_unlock_irqrestore(&pci_lock, flags); \
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return res; \
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}
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#define PCI_OP_WRITE(size,type,len) \
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int pci_bus_write_config_##size \
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(struct pci_bus *bus, unsigned int devfn, int pos, type value) \
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{ \
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int res; \
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unsigned long flags; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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spin_lock_irqsave(&pci_lock, flags); \
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res = bus->ops->write(bus, devfn, pos, len, value); \
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spin_unlock_irqrestore(&pci_lock, flags); \
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return res; \
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}
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PCI_OP_READ(byte, u8, 1)
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PCI_OP_READ(word, u16, 2)
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PCI_OP_READ(dword, u32, 4)
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PCI_OP_WRITE(byte, u8, 1)
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PCI_OP_WRITE(word, u16, 2)
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PCI_OP_WRITE(dword, u32, 4)
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EXPORT_SYMBOL(pci_bus_read_config_byte);
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EXPORT_SYMBOL(pci_bus_read_config_word);
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EXPORT_SYMBOL(pci_bus_read_config_dword);
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EXPORT_SYMBOL(pci_bus_write_config_byte);
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EXPORT_SYMBOL(pci_bus_write_config_word);
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EXPORT_SYMBOL(pci_bus_write_config_dword);
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/*
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* The following routines are to prevent the user from accessing PCI config
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* space when it's unsafe to do so. Some devices require this during BIST and
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* we're required to prevent it during D-state transitions.
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*
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* We have a bit per device to indicate it's blocked and a global wait queue
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* for callers to sleep on until devices are unblocked.
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*/
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static DECLARE_WAIT_QUEUE_HEAD(pci_ucfg_wait);
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static noinline void pci_wait_ucfg(struct pci_dev *dev)
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{
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DECLARE_WAITQUEUE(wait, current);
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__add_wait_queue(&pci_ucfg_wait, &wait);
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do {
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set_current_state(TASK_UNINTERRUPTIBLE);
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spin_unlock_irq(&pci_lock);
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schedule();
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spin_lock_irq(&pci_lock);
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} while (dev->block_ucfg_access);
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__remove_wait_queue(&pci_ucfg_wait, &wait);
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}
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#define PCI_USER_READ_CONFIG(size,type) \
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int pci_user_read_config_##size \
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(struct pci_dev *dev, int pos, type *val) \
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{ \
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int ret = 0; \
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u32 data = -1; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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spin_lock_irq(&pci_lock); \
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if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
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ret = dev->bus->ops->read(dev->bus, dev->devfn, \
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pos, sizeof(type), &data); \
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spin_unlock_irq(&pci_lock); \
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*val = (type)data; \
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return ret; \
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}
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#define PCI_USER_WRITE_CONFIG(size,type) \
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int pci_user_write_config_##size \
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(struct pci_dev *dev, int pos, type val) \
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{ \
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int ret = -EIO; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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spin_lock_irq(&pci_lock); \
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if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
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ret = dev->bus->ops->write(dev->bus, dev->devfn, \
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pos, sizeof(type), val); \
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spin_unlock_irq(&pci_lock); \
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return ret; \
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}
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PCI_USER_READ_CONFIG(byte, u8)
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PCI_USER_READ_CONFIG(word, u16)
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PCI_USER_READ_CONFIG(dword, u32)
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PCI_USER_WRITE_CONFIG(byte, u8)
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PCI_USER_WRITE_CONFIG(word, u16)
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PCI_USER_WRITE_CONFIG(dword, u32)
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/* VPD access through PCI 2.2+ VPD capability */
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#define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
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struct pci_vpd_pci22 {
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struct pci_vpd base;
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spinlock_t lock; /* controls access to hardware and the flags */
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u8 cap;
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bool busy;
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bool flag; /* value of F bit to wait for */
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};
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/* Wait for last operation to complete */
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static int pci_vpd_pci22_wait(struct pci_dev *dev)
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{
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struct pci_vpd_pci22 *vpd =
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container_of(dev->vpd, struct pci_vpd_pci22, base);
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u16 flag, status;
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int wait;
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int ret;
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if (!vpd->busy)
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return 0;
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flag = vpd->flag ? PCI_VPD_ADDR_F : 0;
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wait = vpd->flag ? 10 : 1000; /* read: 100 us; write: 10 ms */
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for (;;) {
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ret = pci_user_read_config_word(dev,
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vpd->cap + PCI_VPD_ADDR,
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&status);
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if (ret < 0)
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return ret;
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if ((status & PCI_VPD_ADDR_F) == flag) {
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vpd->busy = false;
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return 0;
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}
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if (wait-- == 0)
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return -ETIMEDOUT;
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udelay(10);
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}
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}
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static int pci_vpd_pci22_read(struct pci_dev *dev, int pos, int size,
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char *buf)
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{
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struct pci_vpd_pci22 *vpd =
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container_of(dev->vpd, struct pci_vpd_pci22, base);
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u32 val;
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int ret;
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int begin, end, i;
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if (pos < 0 || pos > vpd->base.len || size > vpd->base.len - pos)
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return -EINVAL;
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if (size == 0)
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return 0;
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spin_lock_irq(&vpd->lock);
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ret = pci_vpd_pci22_wait(dev);
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if (ret < 0)
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goto out;
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ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
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pos & ~3);
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if (ret < 0)
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goto out;
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vpd->busy = true;
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vpd->flag = 1;
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ret = pci_vpd_pci22_wait(dev);
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if (ret < 0)
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goto out;
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ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA,
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&val);
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out:
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spin_unlock_irq(&vpd->lock);
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if (ret < 0)
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return ret;
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/* Convert to bytes */
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begin = pos & 3;
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end = min(4, begin + size);
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for (i = 0; i < end; ++i) {
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if (i >= begin)
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*buf++ = val;
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val >>= 8;
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}
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return end - begin;
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}
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static int pci_vpd_pci22_write(struct pci_dev *dev, int pos, int size,
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const char *buf)
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{
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struct pci_vpd_pci22 *vpd =
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container_of(dev->vpd, struct pci_vpd_pci22, base);
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u32 val;
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int ret;
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if (pos < 0 || pos > vpd->base.len || pos & 3 ||
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size > vpd->base.len - pos || size < 4)
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return -EINVAL;
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val = (u8) *buf++;
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val |= ((u8) *buf++) << 8;
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val |= ((u8) *buf++) << 16;
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val |= ((u32)(u8) *buf++) << 24;
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spin_lock_irq(&vpd->lock);
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ret = pci_vpd_pci22_wait(dev);
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if (ret < 0)
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goto out;
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ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA,
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val);
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if (ret < 0)
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goto out;
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ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
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pos | PCI_VPD_ADDR_F);
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if (ret < 0)
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goto out;
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vpd->busy = true;
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vpd->flag = 0;
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ret = pci_vpd_pci22_wait(dev);
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out:
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spin_unlock_irq(&vpd->lock);
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if (ret < 0)
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return ret;
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return 4;
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}
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static void pci_vpd_pci22_release(struct pci_dev *dev)
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{
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kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
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}
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static struct pci_vpd_ops pci_vpd_pci22_ops = {
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.read = pci_vpd_pci22_read,
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.write = pci_vpd_pci22_write,
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.release = pci_vpd_pci22_release,
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};
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int pci_vpd_pci22_init(struct pci_dev *dev)
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{
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struct pci_vpd_pci22 *vpd;
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u8 cap;
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cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
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if (!cap)
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return -ENODEV;
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vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
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if (!vpd)
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return -ENOMEM;
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vpd->base.len = PCI_VPD_PCI22_SIZE;
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vpd->base.ops = &pci_vpd_pci22_ops;
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spin_lock_init(&vpd->lock);
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vpd->cap = cap;
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vpd->busy = false;
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dev->vpd = &vpd->base;
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return 0;
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}
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/**
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* pci_block_user_cfg_access - Block userspace PCI config reads/writes
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* @dev: pci device struct
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*
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* When user access is blocked, any reads or writes to config space will
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* sleep until access is unblocked again. We don't allow nesting of
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* block/unblock calls.
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*/
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void pci_block_user_cfg_access(struct pci_dev *dev)
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{
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unsigned long flags;
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int was_blocked;
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spin_lock_irqsave(&pci_lock, flags);
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was_blocked = dev->block_ucfg_access;
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dev->block_ucfg_access = 1;
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spin_unlock_irqrestore(&pci_lock, flags);
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/* If we BUG() inside the pci_lock, we're guaranteed to hose
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* the machine */
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BUG_ON(was_blocked);
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}
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EXPORT_SYMBOL_GPL(pci_block_user_cfg_access);
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/**
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* pci_unblock_user_cfg_access - Unblock userspace PCI config reads/writes
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* @dev: pci device struct
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*
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* This function allows userspace PCI config accesses to resume.
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*/
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void pci_unblock_user_cfg_access(struct pci_dev *dev)
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{
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unsigned long flags;
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spin_lock_irqsave(&pci_lock, flags);
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/* This indicates a problem in the caller, but we don't need
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* to kill them, unlike a double-block above. */
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WARN_ON(!dev->block_ucfg_access);
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dev->block_ucfg_access = 0;
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wake_up_all(&pci_ucfg_wait);
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spin_unlock_irqrestore(&pci_lock, flags);
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}
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EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access);
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