575 lines
12 KiB
C
575 lines
12 KiB
C
/*
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* Marvell UMI head file
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*
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* Copyright 2011 Marvell. <jyli@marvell.com>
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*
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* This file is licensed under GPLv2.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the
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* License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*/
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#ifndef MVUMI_H
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#define MVUMI_H
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#define MAX_BASE_ADDRESS 6
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#define VER_MAJOR 1
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#define VER_MINOR 1
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#define VER_OEM 0
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#define VER_BUILD 1500
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#define MV_DRIVER_NAME "mvumi"
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#define PCI_VENDOR_ID_MARVELL_2 0x1b4b
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#define PCI_DEVICE_ID_MARVELL_MV9143 0x9143
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#define PCI_DEVICE_ID_MARVELL_MV9580 0x9580
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#define MVUMI_INTERNAL_CMD_WAIT_TIME 45
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#define MVUMI_INQUIRY_LENGTH 44
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#define MVUMI_INQUIRY_UUID_OFF 36
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#define MVUMI_INQUIRY_UUID_LEN 8
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#define IS_DMA64 (sizeof(dma_addr_t) == 8)
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enum mvumi_qc_result {
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MV_QUEUE_COMMAND_RESULT_SENT = 0,
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MV_QUEUE_COMMAND_RESULT_NO_RESOURCE,
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};
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struct mvumi_hw_regs {
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/* For CPU */
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void *main_int_cause_reg;
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void *enpointa_mask_reg;
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void *enpointb_mask_reg;
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void *rstoutn_en_reg;
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void *ctrl_sts_reg;
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void *rstoutn_mask_reg;
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void *sys_soft_rst_reg;
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/* For Doorbell */
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void *pciea_to_arm_drbl_reg;
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void *arm_to_pciea_drbl_reg;
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void *arm_to_pciea_mask_reg;
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void *pciea_to_arm_msg0;
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void *pciea_to_arm_msg1;
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void *arm_to_pciea_msg0;
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void *arm_to_pciea_msg1;
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/* reset register */
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void *reset_request;
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void *reset_enable;
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/* For Message Unit */
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void *inb_list_basel;
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void *inb_list_baseh;
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void *inb_aval_count_basel;
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void *inb_aval_count_baseh;
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void *inb_write_pointer;
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void *inb_read_pointer;
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void *outb_list_basel;
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void *outb_list_baseh;
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void *outb_copy_basel;
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void *outb_copy_baseh;
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void *outb_copy_pointer;
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void *outb_read_pointer;
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void *inb_isr_cause;
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void *outb_isr_cause;
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void *outb_coal_cfg;
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void *outb_coal_timeout;
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/* Bit setting for HW */
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u32 int_comaout;
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u32 int_comaerr;
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u32 int_dl_cpu2pciea;
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u32 int_mu;
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u32 int_drbl_int_mask;
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u32 int_main_int_mask;
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u32 cl_pointer_toggle;
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u32 cl_slot_num_mask;
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u32 clic_irq;
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u32 clic_in_err;
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u32 clic_out_err;
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};
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struct mvumi_dyn_list_entry {
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u32 src_low_addr;
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u32 src_high_addr;
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u32 if_length;
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u32 reserve;
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};
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#define SCSI_CMD_MARVELL_SPECIFIC 0xE1
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#define CDB_CORE_MODULE 0x1
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#define CDB_CORE_SHUTDOWN 0xB
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enum {
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DRBL_HANDSHAKE = 1 << 0,
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DRBL_SOFT_RESET = 1 << 1,
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DRBL_BUS_CHANGE = 1 << 2,
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DRBL_EVENT_NOTIFY = 1 << 3,
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DRBL_MU_RESET = 1 << 4,
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DRBL_HANDSHAKE_ISR = DRBL_HANDSHAKE,
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/*
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* Command flag is the flag for the CDB command itself
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*/
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/* 1-non data; 0-data command */
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CMD_FLAG_NON_DATA = 1 << 0,
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CMD_FLAG_DMA = 1 << 1,
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CMD_FLAG_PIO = 1 << 2,
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/* 1-host read data */
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CMD_FLAG_DATA_IN = 1 << 3,
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/* 1-host write data */
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CMD_FLAG_DATA_OUT = 1 << 4,
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CMD_FLAG_PRDT_IN_HOST = 1 << 5,
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};
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#define APICDB0_EVENT 0xF4
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#define APICDB1_EVENT_GETEVENT 0
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#define APICDB1_HOST_GETEVENT 1
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#define MAX_EVENTS_RETURNED 6
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#define DEVICE_OFFLINE 0
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#define DEVICE_ONLINE 1
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struct mvumi_hotplug_event {
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u16 size;
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u8 dummy[2];
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u8 bitmap[0];
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};
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struct mvumi_driver_event {
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u32 time_stamp;
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u32 sequence_no;
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u32 event_id;
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u8 severity;
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u8 param_count;
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u16 device_id;
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u32 params[4];
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u8 sense_data_length;
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u8 Reserved1;
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u8 sense_data[30];
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};
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struct mvumi_event_req {
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unsigned char count;
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unsigned char reserved[3];
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struct mvumi_driver_event events[MAX_EVENTS_RETURNED];
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};
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struct mvumi_events_wq {
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struct work_struct work_q;
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struct mvumi_hba *mhba;
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unsigned int event;
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void *param;
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};
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#define HS_CAPABILITY_SUPPORT_COMPACT_SG (1U << 4)
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#define HS_CAPABILITY_SUPPORT_PRD_HOST (1U << 5)
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#define HS_CAPABILITY_SUPPORT_DYN_SRC (1U << 6)
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#define HS_CAPABILITY_NEW_PAGE_IO_DEPTH_DEF (1U << 14)
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#define MVUMI_MAX_SG_ENTRY 32
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#define SGD_EOT (1L << 27)
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#define SGD_EOT_CP (1L << 22)
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struct mvumi_sgl {
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u32 baseaddr_l;
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u32 baseaddr_h;
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u32 flags;
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u32 size;
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};
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struct mvumi_compact_sgl {
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u32 baseaddr_l;
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u32 baseaddr_h;
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u32 flags;
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};
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#define GET_COMPACT_SGD_SIZE(sgd) \
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((((struct mvumi_compact_sgl *)(sgd))->flags) & 0x3FFFFFL)
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#define SET_COMPACT_SGD_SIZE(sgd, sz) do { \
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(((struct mvumi_compact_sgl *)(sgd))->flags) &= ~0x3FFFFFL; \
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(((struct mvumi_compact_sgl *)(sgd))->flags) |= (sz); \
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} while (0)
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#define sgd_getsz(_mhba, sgd, sz) do { \
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if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \
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(sz) = GET_COMPACT_SGD_SIZE(sgd); \
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else \
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(sz) = (sgd)->size; \
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} while (0)
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#define sgd_setsz(_mhba, sgd, sz) do { \
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if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \
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SET_COMPACT_SGD_SIZE(sgd, sz); \
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else \
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(sgd)->size = (sz); \
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} while (0)
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#define sgd_inc(_mhba, sgd) do { \
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if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \
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sgd = (struct mvumi_sgl *)(((unsigned char *) (sgd)) + 12); \
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else \
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sgd = (struct mvumi_sgl *)(((unsigned char *) (sgd)) + 16); \
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} while (0)
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struct mvumi_res {
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struct list_head entry;
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dma_addr_t bus_addr;
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void *virt_addr;
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unsigned int size;
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unsigned short type; /* enum Resource_Type */
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};
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/* Resource type */
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enum resource_type {
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RESOURCE_CACHED_MEMORY = 0,
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RESOURCE_UNCACHED_MEMORY
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};
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struct mvumi_sense_data {
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u8 error_code:7;
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u8 valid:1;
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u8 segment_number;
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u8 sense_key:4;
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u8 reserved:1;
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u8 incorrect_length:1;
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u8 end_of_media:1;
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u8 file_mark:1;
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u8 information[4];
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u8 additional_sense_length;
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u8 command_specific_information[4];
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u8 additional_sense_code;
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u8 additional_sense_code_qualifier;
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u8 field_replaceable_unit_code;
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u8 sense_key_specific[3];
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};
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/* Request initiator must set the status to REQ_STATUS_PENDING. */
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#define REQ_STATUS_PENDING 0x80
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struct mvumi_cmd {
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struct list_head queue_pointer;
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struct mvumi_msg_frame *frame;
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dma_addr_t frame_phys;
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struct scsi_cmnd *scmd;
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atomic_t sync_cmd;
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void *data_buf;
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unsigned short request_id;
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unsigned char cmd_status;
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};
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/*
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* the function type of the in bound frame
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*/
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#define CL_FUN_SCSI_CMD 0x1
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struct mvumi_msg_frame {
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u16 device_id;
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u16 tag;
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u8 cmd_flag;
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u8 req_function;
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u8 cdb_length;
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u8 sg_counts;
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u32 data_transfer_length;
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u16 request_id;
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u16 reserved1;
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u8 cdb[MAX_COMMAND_SIZE];
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u32 payload[1];
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};
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/*
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* the respond flag for data_payload of the out bound frame
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*/
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#define CL_RSP_FLAG_NODATA 0x0
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#define CL_RSP_FLAG_SENSEDATA 0x1
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struct mvumi_rsp_frame {
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u16 device_id;
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u16 tag;
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u8 req_status;
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u8 rsp_flag; /* Indicates the type of Data_Payload.*/
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u16 request_id;
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u32 payload[1];
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};
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struct mvumi_ob_data {
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struct list_head list;
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unsigned char data[0];
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};
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struct version_info {
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u32 ver_major;
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u32 ver_minor;
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u32 ver_oem;
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u32 ver_build;
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};
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#define FW_MAX_DELAY 30
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#define MVUMI_FW_BUSY (1U << 0)
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#define MVUMI_FW_ATTACH (1U << 1)
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#define MVUMI_FW_ALLOC (1U << 2)
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/*
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* State is the state of the MU
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*/
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#define FW_STATE_IDLE 0
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#define FW_STATE_STARTING 1
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#define FW_STATE_HANDSHAKING 2
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#define FW_STATE_STARTED 3
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#define FW_STATE_ABORT 4
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#define HANDSHAKE_SIGNATURE 0x5A5A5A5AL
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#define HANDSHAKE_READYSTATE 0x55AA5AA5L
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#define HANDSHAKE_DONESTATE 0x55AAA55AL
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/* HandShake Status definition */
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#define HS_STATUS_OK 1
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#define HS_STATUS_ERR 2
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#define HS_STATUS_INVALID 3
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/* HandShake State/Cmd definition */
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#define HS_S_START 1
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#define HS_S_RESET 2
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#define HS_S_PAGE_ADDR 3
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#define HS_S_QUERY_PAGE 4
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#define HS_S_SEND_PAGE 5
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#define HS_S_END 6
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#define HS_S_ABORT 7
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#define HS_PAGE_VERIFY_SIZE 128
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#define HS_GET_STATE(a) (a & 0xFFFF)
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#define HS_GET_STATUS(a) ((a & 0xFFFF0000) >> 16)
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#define HS_SET_STATE(a, b) (a |= (b & 0xFFFF))
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#define HS_SET_STATUS(a, b) (a |= ((b & 0xFFFF) << 16))
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/* handshake frame */
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struct mvumi_hs_frame {
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u16 size;
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/* host information */
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u8 host_type;
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u8 reserved_1[1];
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struct version_info host_ver; /* bios or driver version */
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/* controller information */
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u32 system_io_bus;
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u32 slot_number;
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u32 intr_level;
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u32 intr_vector;
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/* communication list configuration */
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u32 ib_baseaddr_l;
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u32 ib_baseaddr_h;
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u32 ob_baseaddr_l;
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u32 ob_baseaddr_h;
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u8 ib_entry_size;
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u8 ob_entry_size;
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u8 ob_depth;
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u8 ib_depth;
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/* system time */
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u64 seconds_since1970;
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};
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struct mvumi_hs_header {
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u8 page_code;
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u8 checksum;
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u16 frame_length;
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u32 frame_content[1];
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};
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/*
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* the page code type of the handshake header
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*/
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#define HS_PAGE_FIRM_CAP 0x1
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#define HS_PAGE_HOST_INFO 0x2
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#define HS_PAGE_FIRM_CTL 0x3
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#define HS_PAGE_CL_INFO 0x4
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#define HS_PAGE_TOTAL 0x5
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#define HSP_SIZE(i) sizeof(struct mvumi_hs_page##i)
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#define HSP_MAX_SIZE ({ \
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int size, m1, m2; \
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m1 = max(HSP_SIZE(1), HSP_SIZE(3)); \
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m2 = max(HSP_SIZE(2), HSP_SIZE(4)); \
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size = max(m1, m2); \
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size; \
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})
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/* The format of the page code for Firmware capability */
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struct mvumi_hs_page1 {
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u8 pagecode;
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u8 checksum;
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u16 frame_length;
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u16 number_of_ports;
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u16 max_devices_support;
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u16 max_io_support;
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u16 umi_ver;
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u32 max_transfer_size;
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struct version_info fw_ver;
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u8 cl_in_max_entry_size;
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u8 cl_out_max_entry_size;
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u8 cl_inout_list_depth;
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u8 total_pages;
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u16 capability;
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u16 reserved1;
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};
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/* The format of the page code for Host information */
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struct mvumi_hs_page2 {
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u8 pagecode;
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u8 checksum;
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u16 frame_length;
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u8 host_type;
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u8 host_cap;
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u8 reserved[2];
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struct version_info host_ver;
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u32 system_io_bus;
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u32 slot_number;
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u32 intr_level;
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u32 intr_vector;
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u64 seconds_since1970;
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};
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/* The format of the page code for firmware control */
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struct mvumi_hs_page3 {
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u8 pagecode;
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u8 checksum;
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u16 frame_length;
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u16 control;
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u8 reserved[2];
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u32 host_bufferaddr_l;
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u32 host_bufferaddr_h;
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u32 host_eventaddr_l;
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u32 host_eventaddr_h;
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};
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struct mvumi_hs_page4 {
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u8 pagecode;
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u8 checksum;
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u16 frame_length;
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u32 ib_baseaddr_l;
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u32 ib_baseaddr_h;
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u32 ob_baseaddr_l;
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u32 ob_baseaddr_h;
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u8 ib_entry_size;
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u8 ob_entry_size;
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u8 ob_depth;
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u8 ib_depth;
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};
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struct mvumi_tag {
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unsigned short *stack;
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unsigned short top;
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unsigned short size;
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};
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struct mvumi_device {
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struct list_head list;
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struct scsi_device *sdev;
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u64 wwid;
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u8 dev_type;
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int id;
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};
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struct mvumi_hba {
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void *base_addr[MAX_BASE_ADDRESS];
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u32 pci_base[MAX_BASE_ADDRESS];
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void *mmio;
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struct list_head cmd_pool;
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struct Scsi_Host *shost;
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wait_queue_head_t int_cmd_wait_q;
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struct pci_dev *pdev;
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unsigned int unique_id;
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atomic_t fw_outstanding;
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struct mvumi_instance_template *instancet;
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void *ib_list;
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dma_addr_t ib_list_phys;
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void *ib_frame;
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dma_addr_t ib_frame_phys;
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void *ob_list;
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dma_addr_t ob_list_phys;
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void *ib_shadow;
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dma_addr_t ib_shadow_phys;
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void *ob_shadow;
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dma_addr_t ob_shadow_phys;
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void *handshake_page;
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dma_addr_t handshake_page_phys;
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unsigned int global_isr;
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unsigned int isr_status;
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unsigned short max_sge;
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unsigned short max_target_id;
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unsigned char *target_map;
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unsigned int max_io;
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unsigned int list_num_io;
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unsigned int ib_max_size;
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unsigned int ob_max_size;
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unsigned int ib_max_size_setting;
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unsigned int ob_max_size_setting;
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unsigned int max_transfer_size;
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unsigned char hba_total_pages;
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unsigned char fw_flag;
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unsigned char request_id_enabled;
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unsigned char eot_flag;
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unsigned short hba_capability;
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unsigned short io_seq;
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unsigned int ib_cur_slot;
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unsigned int ob_cur_slot;
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unsigned int fw_state;
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struct mutex sas_discovery_mutex;
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struct list_head ob_data_list;
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struct list_head free_ob_list;
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struct list_head res_list;
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struct list_head waiting_req_list;
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struct mvumi_tag tag_pool;
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struct mvumi_cmd **tag_cmd;
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struct mvumi_hw_regs *regs;
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struct mutex device_lock;
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struct list_head mhba_dev_list;
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struct list_head shost_dev_list;
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struct task_struct *dm_thread;
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atomic_t pnp_count;
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};
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struct mvumi_instance_template {
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void (*fire_cmd) (struct mvumi_hba *, struct mvumi_cmd *);
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void (*enable_intr) (struct mvumi_hba *);
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void (*disable_intr) (struct mvumi_hba *);
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int (*clear_intr) (void *);
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unsigned int (*read_fw_status_reg) (struct mvumi_hba *);
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unsigned int (*check_ib_list) (struct mvumi_hba *);
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int (*check_ob_list) (struct mvumi_hba *, unsigned int *,
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unsigned int *);
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int (*reset_host) (struct mvumi_hba *);
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};
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extern struct timezone sys_tz;
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#endif
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