325 lines
8.8 KiB
C
325 lines
8.8 KiB
C
#include "radeonfb.h"
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/* the accelerated functions here are patterned after the
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* "ACCEL_MMIO" ifdef branches in XFree86
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* --dte
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*/
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static void radeon_fixup_offset(struct radeonfb_info *rinfo)
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{
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u32 local_base;
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/* *** Ugly workaround *** */
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/*
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* On some platforms, the video memory is mapped at 0 in radeon chip space
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* (like PPCs) by the firmware. X will always move it up so that it's seen
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* by the chip to be at the same address as the PCI BAR.
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* That means that when switching back from X, there is a mismatch between
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* the offsets programmed into the engine. This means that potentially,
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* accel operations done before radeonfb has a chance to re-init the engine
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* will have incorrect offsets, and potentially trash system memory !
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*
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* The correct fix is for fbcon to never call any accel op before the engine
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* has properly been re-initialized (by a call to set_var), but this is a
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* complex fix. This workaround in the meantime, called before every accel
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* operation, makes sure the offsets are in sync.
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*/
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radeon_fifo_wait (1);
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local_base = INREG(MC_FB_LOCATION) << 16;
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if (local_base == rinfo->fb_local_base)
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return;
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rinfo->fb_local_base = local_base;
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radeon_fifo_wait (3);
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OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
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(rinfo->fb_local_base >> 10));
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OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
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OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
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}
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static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo,
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const struct fb_fillrect *region)
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{
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radeon_fifo_wait(4);
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OUTREG(DP_GUI_MASTER_CNTL,
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rinfo->dp_gui_master_cntl /* contains, like GMC_DST_32BPP */
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| GMC_BRUSH_SOLID_COLOR
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| ROP3_P);
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if (radeon_get_dstbpp(rinfo->depth) != DST_8BPP)
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OUTREG(DP_BRUSH_FRGD_CLR, rinfo->pseudo_palette[region->color]);
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else
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OUTREG(DP_BRUSH_FRGD_CLR, region->color);
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OUTREG(DP_WRITE_MSK, 0xffffffff);
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OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
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radeon_fifo_wait(2);
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OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
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OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
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radeon_fifo_wait(2);
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OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
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OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
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}
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void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
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{
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struct radeonfb_info *rinfo = info->par;
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struct fb_fillrect modded;
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int vxres, vyres;
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if (info->state != FBINFO_STATE_RUNNING)
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return;
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if (info->flags & FBINFO_HWACCEL_DISABLED) {
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cfb_fillrect(info, region);
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return;
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}
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radeon_fixup_offset(rinfo);
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vxres = info->var.xres_virtual;
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vyres = info->var.yres_virtual;
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memcpy(&modded, region, sizeof(struct fb_fillrect));
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if(!modded.width || !modded.height ||
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modded.dx >= vxres || modded.dy >= vyres)
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return;
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if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
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if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
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radeonfb_prim_fillrect(rinfo, &modded);
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}
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static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo,
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const struct fb_copyarea *area)
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{
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int xdir, ydir;
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u32 sx, sy, dx, dy, w, h;
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w = area->width; h = area->height;
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dx = area->dx; dy = area->dy;
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sx = area->sx; sy = area->sy;
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xdir = sx - dx;
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ydir = sy - dy;
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if ( xdir < 0 ) { sx += w-1; dx += w-1; }
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if ( ydir < 0 ) { sy += h-1; dy += h-1; }
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radeon_fifo_wait(3);
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OUTREG(DP_GUI_MASTER_CNTL,
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rinfo->dp_gui_master_cntl /* i.e. GMC_DST_32BPP */
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| GMC_BRUSH_NONE
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| GMC_SRC_DSTCOLOR
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| ROP3_S
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| DP_SRC_SOURCE_MEMORY );
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OUTREG(DP_WRITE_MSK, 0xffffffff);
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OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0)
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| (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));
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radeon_fifo_wait(2);
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OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
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OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
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radeon_fifo_wait(3);
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OUTREG(SRC_Y_X, (sy << 16) | sx);
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OUTREG(DST_Y_X, (dy << 16) | dx);
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OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w);
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}
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void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
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{
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struct radeonfb_info *rinfo = info->par;
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struct fb_copyarea modded;
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u32 vxres, vyres;
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modded.sx = area->sx;
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modded.sy = area->sy;
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modded.dx = area->dx;
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modded.dy = area->dy;
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modded.width = area->width;
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modded.height = area->height;
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if (info->state != FBINFO_STATE_RUNNING)
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return;
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if (info->flags & FBINFO_HWACCEL_DISABLED) {
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cfb_copyarea(info, area);
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return;
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}
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radeon_fixup_offset(rinfo);
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vxres = info->var.xres_virtual;
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vyres = info->var.yres_virtual;
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if(!modded.width || !modded.height ||
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modded.sx >= vxres || modded.sy >= vyres ||
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modded.dx >= vxres || modded.dy >= vyres)
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return;
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if(modded.sx + modded.width > vxres) modded.width = vxres - modded.sx;
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if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
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if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy;
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if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
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radeonfb_prim_copyarea(rinfo, &modded);
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}
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void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image)
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{
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struct radeonfb_info *rinfo = info->par;
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if (info->state != FBINFO_STATE_RUNNING)
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return;
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radeon_engine_idle();
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cfb_imageblit(info, image);
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}
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int radeonfb_sync(struct fb_info *info)
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{
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struct radeonfb_info *rinfo = info->par;
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if (info->state != FBINFO_STATE_RUNNING)
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return 0;
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radeon_engine_idle();
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return 0;
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}
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void radeonfb_engine_reset(struct radeonfb_info *rinfo)
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{
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u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
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u32 host_path_cntl;
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radeon_engine_flush (rinfo);
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clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
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mclk_cntl = INPLL(MCLK_CNTL);
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OUTPLL(MCLK_CNTL, (mclk_cntl |
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FORCEON_MCLKA |
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FORCEON_MCLKB |
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FORCEON_YCLKA |
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FORCEON_YCLKB |
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FORCEON_MC |
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FORCEON_AIC));
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host_path_cntl = INREG(HOST_PATH_CNTL);
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rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
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if (rinfo->family == CHIP_FAMILY_R300 ||
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rinfo->family == CHIP_FAMILY_R350 ||
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rinfo->family == CHIP_FAMILY_RV350) {
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u32 tmp;
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OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset |
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SOFT_RESET_CP |
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SOFT_RESET_HI |
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SOFT_RESET_E2));
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INREG(RBBM_SOFT_RESET);
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OUTREG(RBBM_SOFT_RESET, 0);
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tmp = INREG(RB2D_DSTCACHE_MODE);
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OUTREG(RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */
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} else {
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OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
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SOFT_RESET_CP |
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SOFT_RESET_HI |
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SOFT_RESET_SE |
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SOFT_RESET_RE |
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SOFT_RESET_PP |
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SOFT_RESET_E2 |
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SOFT_RESET_RB);
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INREG(RBBM_SOFT_RESET);
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OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
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~(SOFT_RESET_CP |
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SOFT_RESET_HI |
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SOFT_RESET_SE |
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SOFT_RESET_RE |
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SOFT_RESET_PP |
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SOFT_RESET_E2 |
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SOFT_RESET_RB));
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INREG(RBBM_SOFT_RESET);
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}
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OUTREG(HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET);
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INREG(HOST_PATH_CNTL);
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OUTREG(HOST_PATH_CNTL, host_path_cntl);
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if (rinfo->family != CHIP_FAMILY_R300 &&
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rinfo->family != CHIP_FAMILY_R350 &&
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rinfo->family != CHIP_FAMILY_RV350)
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OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
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OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
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OUTPLL(MCLK_CNTL, mclk_cntl);
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}
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void radeonfb_engine_init (struct radeonfb_info *rinfo)
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{
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unsigned long temp;
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/* disable 3D engine */
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OUTREG(RB3D_CNTL, 0);
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radeonfb_engine_reset(rinfo);
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radeon_fifo_wait (1);
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if ((rinfo->family != CHIP_FAMILY_R300) &&
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(rinfo->family != CHIP_FAMILY_R350) &&
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(rinfo->family != CHIP_FAMILY_RV350))
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OUTREG(RB2D_DSTCACHE_MODE, 0);
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radeon_fifo_wait (3);
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/* We re-read MC_FB_LOCATION from card as it can have been
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* modified by XFree drivers (ouch !)
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*/
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rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
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OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
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(rinfo->fb_local_base >> 10));
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OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
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OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
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radeon_fifo_wait (1);
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#if defined(__BIG_ENDIAN)
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OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
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#else
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OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
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#endif
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radeon_fifo_wait (2);
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OUTREG(DEFAULT_SC_TOP_LEFT, 0);
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OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
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DEFAULT_SC_BOTTOM_MAX));
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temp = radeon_get_dstbpp(rinfo->depth);
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rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
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radeon_fifo_wait (1);
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OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
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GMC_BRUSH_SOLID_COLOR |
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GMC_SRC_DATATYPE_COLOR));
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radeon_fifo_wait (7);
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/* clear line drawing regs */
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OUTREG(DST_LINE_START, 0);
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OUTREG(DST_LINE_END, 0);
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/* set brush color regs */
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OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
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OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
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/* set source color regs */
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OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
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OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
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/* default write mask */
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OUTREG(DP_WRITE_MSK, 0xffffffff);
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radeon_engine_idle ();
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}
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