340 lines
7.1 KiB
C
340 lines
7.1 KiB
C
/* pcr.c: Generic sparc64 performance counter infrastructure.
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*
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* Copyright (C) 2009 David S. Miller (davem@davemloft.net)
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*/
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irq_work.h>
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#include <linux/ftrace.h>
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#include <asm/pil.h>
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#include <asm/pcr.h>
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#include <asm/nmi.h>
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#include <asm/asi.h>
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#include <asm/spitfire.h>
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/* This code is shared between various users of the performance
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* counters. Users will be oprofile, pseudo-NMI watchdog, and the
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* perf_event support layer.
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*/
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/* Performance counter interrupts run unmasked at PIL level 15.
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* Therefore we can't do things like wakeups and other work
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* that expects IRQ disabling to be adhered to in locking etc.
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*
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* Therefore in such situations we defer the work by signalling
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* a lower level cpu IRQ.
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*/
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void __irq_entry deferred_pcr_work_irq(int irq, struct pt_regs *regs)
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{
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struct pt_regs *old_regs;
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clear_softint(1 << PIL_DEFERRED_PCR_WORK);
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old_regs = set_irq_regs(regs);
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irq_enter();
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#ifdef CONFIG_IRQ_WORK
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irq_work_run();
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#endif
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irq_exit();
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set_irq_regs(old_regs);
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}
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void arch_irq_work_raise(void)
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{
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set_softint(1 << PIL_DEFERRED_PCR_WORK);
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}
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const struct pcr_ops *pcr_ops;
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EXPORT_SYMBOL_GPL(pcr_ops);
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static u64 direct_pcr_read(unsigned long reg_num)
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{
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u64 val;
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WARN_ON_ONCE(reg_num != 0);
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__asm__ __volatile__("rd %%pcr, %0" : "=r" (val));
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return val;
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}
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static void direct_pcr_write(unsigned long reg_num, u64 val)
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{
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WARN_ON_ONCE(reg_num != 0);
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__asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (val));
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}
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static u64 direct_pic_read(unsigned long reg_num)
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{
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u64 val;
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WARN_ON_ONCE(reg_num != 0);
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__asm__ __volatile__("rd %%pic, %0" : "=r" (val));
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return val;
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}
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static void direct_pic_write(unsigned long reg_num, u64 val)
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{
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WARN_ON_ONCE(reg_num != 0);
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/* Blackbird errata workaround. See commentary in
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* arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
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* for more information.
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*/
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__asm__ __volatile__("ba,pt %%xcc, 99f\n\t"
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" nop\n\t"
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".align 64\n"
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"99:wr %0, 0x0, %%pic\n\t"
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"rd %%pic, %%g0" : : "r" (val));
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}
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static u64 direct_picl_value(unsigned int nmi_hz)
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{
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u32 delta = local_cpu_data().clock_tick / nmi_hz;
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return ((u64)((0 - delta) & 0xffffffff)) << 32;
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}
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static const struct pcr_ops direct_pcr_ops = {
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.read_pcr = direct_pcr_read,
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.write_pcr = direct_pcr_write,
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.read_pic = direct_pic_read,
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.write_pic = direct_pic_write,
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.nmi_picl_value = direct_picl_value,
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.pcr_nmi_enable = (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE),
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.pcr_nmi_disable = PCR_PIC_PRIV,
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};
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static void n2_pcr_write(unsigned long reg_num, u64 val)
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{
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unsigned long ret;
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WARN_ON_ONCE(reg_num != 0);
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if (val & PCR_N2_HTRACE) {
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ret = sun4v_niagara2_setperf(HV_N2_PERF_SPARC_CTL, val);
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if (ret != HV_EOK)
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direct_pcr_write(reg_num, val);
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} else
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direct_pcr_write(reg_num, val);
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}
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static u64 n2_picl_value(unsigned int nmi_hz)
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{
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u32 delta = local_cpu_data().clock_tick / (nmi_hz << 2);
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return ((u64)((0 - delta) & 0xffffffff)) << 32;
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}
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static const struct pcr_ops n2_pcr_ops = {
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.read_pcr = direct_pcr_read,
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.write_pcr = n2_pcr_write,
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.read_pic = direct_pic_read,
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.write_pic = direct_pic_write,
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.nmi_picl_value = n2_picl_value,
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.pcr_nmi_enable = (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE |
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PCR_N2_TOE_OV1 |
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(2 << PCR_N2_SL1_SHIFT) |
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(0xff << PCR_N2_MASK1_SHIFT)),
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.pcr_nmi_disable = PCR_PIC_PRIV,
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};
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static u64 n4_pcr_read(unsigned long reg_num)
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{
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unsigned long val;
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(void) sun4v_vt_get_perfreg(reg_num, &val);
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return val;
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}
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static void n4_pcr_write(unsigned long reg_num, u64 val)
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{
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(void) sun4v_vt_set_perfreg(reg_num, val);
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}
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static u64 n4_pic_read(unsigned long reg_num)
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{
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unsigned long val;
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__asm__ __volatile__("ldxa [%1] %2, %0"
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: "=r" (val)
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: "r" (reg_num * 0x8UL), "i" (ASI_PIC));
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return val;
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}
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static void n4_pic_write(unsigned long reg_num, u64 val)
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{
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__asm__ __volatile__("stxa %0, [%1] %2"
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: /* no outputs */
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: "r" (val), "r" (reg_num * 0x8UL), "i" (ASI_PIC));
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}
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static u64 n4_picl_value(unsigned int nmi_hz)
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{
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u32 delta = local_cpu_data().clock_tick / (nmi_hz << 2);
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return ((u64)((0 - delta) & 0xffffffff));
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}
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static const struct pcr_ops n4_pcr_ops = {
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.read_pcr = n4_pcr_read,
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.write_pcr = n4_pcr_write,
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.read_pic = n4_pic_read,
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.write_pic = n4_pic_write,
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.nmi_picl_value = n4_picl_value,
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.pcr_nmi_enable = (PCR_N4_PICNPT | PCR_N4_STRACE |
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PCR_N4_UTRACE | PCR_N4_TOE |
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(26 << PCR_N4_SL_SHIFT)),
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.pcr_nmi_disable = PCR_N4_PICNPT,
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};
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static u64 n5_pcr_read(unsigned long reg_num)
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{
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unsigned long val;
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(void) sun4v_t5_get_perfreg(reg_num, &val);
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return val;
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}
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static void n5_pcr_write(unsigned long reg_num, u64 val)
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{
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(void) sun4v_t5_set_perfreg(reg_num, val);
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}
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static const struct pcr_ops n5_pcr_ops = {
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.read_pcr = n5_pcr_read,
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.write_pcr = n5_pcr_write,
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.read_pic = n4_pic_read,
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.write_pic = n4_pic_write,
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.nmi_picl_value = n4_picl_value,
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.pcr_nmi_enable = (PCR_N4_PICNPT | PCR_N4_STRACE |
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PCR_N4_UTRACE | PCR_N4_TOE |
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(26 << PCR_N4_SL_SHIFT)),
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.pcr_nmi_disable = PCR_N4_PICNPT,
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};
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static unsigned long perf_hsvc_group;
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static unsigned long perf_hsvc_major;
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static unsigned long perf_hsvc_minor;
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static int __init register_perf_hsvc(void)
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{
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unsigned long hverror;
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if (tlb_type == hypervisor) {
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switch (sun4v_chip_type) {
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case SUN4V_CHIP_NIAGARA1:
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perf_hsvc_group = HV_GRP_NIAG_PERF;
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break;
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case SUN4V_CHIP_NIAGARA2:
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perf_hsvc_group = HV_GRP_N2_CPU;
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break;
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case SUN4V_CHIP_NIAGARA3:
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perf_hsvc_group = HV_GRP_KT_CPU;
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break;
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case SUN4V_CHIP_NIAGARA4:
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perf_hsvc_group = HV_GRP_VT_CPU;
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break;
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case SUN4V_CHIP_NIAGARA5:
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perf_hsvc_group = HV_GRP_T5_CPU;
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break;
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default:
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return -ENODEV;
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}
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perf_hsvc_major = 1;
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perf_hsvc_minor = 0;
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hverror = sun4v_hvapi_register(perf_hsvc_group,
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perf_hsvc_major,
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&perf_hsvc_minor);
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if (hverror) {
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pr_err("perfmon: Could not register hvapi(0x%lx).\n",
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hverror);
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return -ENODEV;
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}
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}
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return 0;
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}
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static void __init unregister_perf_hsvc(void)
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{
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if (tlb_type != hypervisor)
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return;
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sun4v_hvapi_unregister(perf_hsvc_group);
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}
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static int __init setup_sun4v_pcr_ops(void)
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{
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int ret = 0;
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switch (sun4v_chip_type) {
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case SUN4V_CHIP_NIAGARA1:
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case SUN4V_CHIP_NIAGARA2:
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case SUN4V_CHIP_NIAGARA3:
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pcr_ops = &n2_pcr_ops;
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break;
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case SUN4V_CHIP_NIAGARA4:
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pcr_ops = &n4_pcr_ops;
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break;
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case SUN4V_CHIP_NIAGARA5:
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pcr_ops = &n5_pcr_ops;
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break;
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default:
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ret = -ENODEV;
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break;
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}
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return ret;
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}
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int __init pcr_arch_init(void)
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{
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int err = register_perf_hsvc();
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if (err)
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return err;
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switch (tlb_type) {
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case hypervisor:
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err = setup_sun4v_pcr_ops();
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if (err)
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goto out_unregister;
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break;
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case cheetah:
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case cheetah_plus:
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pcr_ops = &direct_pcr_ops;
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break;
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case spitfire:
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/* UltraSPARC-I/II and derivatives lack a profile
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* counter overflow interrupt so we can't make use of
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* their hardware currently.
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*/
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/* fallthrough */
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default:
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err = -ENODEV;
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goto out_unregister;
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}
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return nmi_init();
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out_unregister:
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unregister_perf_hsvc();
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return err;
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}
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