452 lines
11 KiB
C
452 lines
11 KiB
C
/*
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* tegra20_ac97.c - Tegra20 AC97 platform driver
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*
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* Copyright (c) 2012 Lucas Stach <dev@lynxeye.de>
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*
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* Partly based on code copyright/by:
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*
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* Copyright (c) 2011,2012 Toradex Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/dmaengine_pcm.h>
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#include "tegra20_ac97.h"
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#define DRV_NAME "tegra20-ac97"
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static struct tegra20_ac97 *workdata;
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static void tegra20_ac97_codec_reset(struct snd_ac97 *ac97)
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{
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u32 readback;
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unsigned long timeout;
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/* reset line is not driven by DAC pad group, have to toggle GPIO */
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gpio_set_value(workdata->reset_gpio, 0);
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udelay(2);
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gpio_set_value(workdata->reset_gpio, 1);
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udelay(2);
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timeout = jiffies + msecs_to_jiffies(100);
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do {
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regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
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if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
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break;
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usleep_range(1000, 2000);
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} while (!time_after(jiffies, timeout));
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}
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static void tegra20_ac97_codec_warm_reset(struct snd_ac97 *ac97)
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{
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u32 readback;
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unsigned long timeout;
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/*
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* although sync line is driven by the DAC pad group warm reset using
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* the controller cmd is not working, have to toggle sync line
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* manually.
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*/
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gpio_request(workdata->sync_gpio, "codec-sync");
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gpio_direction_output(workdata->sync_gpio, 1);
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udelay(2);
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gpio_set_value(workdata->sync_gpio, 0);
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udelay(2);
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gpio_free(workdata->sync_gpio);
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timeout = jiffies + msecs_to_jiffies(100);
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do {
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regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
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if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
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break;
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usleep_range(1000, 2000);
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} while (!time_after(jiffies, timeout));
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}
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static unsigned short tegra20_ac97_codec_read(struct snd_ac97 *ac97_snd,
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unsigned short reg)
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{
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u32 readback;
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unsigned long timeout;
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regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
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(((reg | 0x80) << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
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TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
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TEGRA20_AC97_CMD_BUSY);
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timeout = jiffies + msecs_to_jiffies(100);
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do {
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regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
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if (readback & TEGRA20_AC97_STATUS1_STA_VALID1)
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break;
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usleep_range(1000, 2000);
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} while (!time_after(jiffies, timeout));
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return ((readback & TEGRA20_AC97_STATUS1_STA_DATA1_MASK) >>
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TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT);
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}
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static void tegra20_ac97_codec_write(struct snd_ac97 *ac97_snd,
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unsigned short reg, unsigned short val)
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{
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u32 readback;
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unsigned long timeout;
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regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
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((reg << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
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TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
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((val << TEGRA20_AC97_CMD_CMD_DATA_SHIFT) &
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TEGRA20_AC97_CMD_CMD_DATA_MASK) |
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TEGRA20_AC97_CMD_BUSY);
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timeout = jiffies + msecs_to_jiffies(100);
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do {
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regmap_read(workdata->regmap, TEGRA20_AC97_CMD, &readback);
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if (!(readback & TEGRA20_AC97_CMD_BUSY))
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break;
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usleep_range(1000, 2000);
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} while (!time_after(jiffies, timeout));
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}
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static struct snd_ac97_bus_ops tegra20_ac97_ops = {
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.read = tegra20_ac97_codec_read,
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.write = tegra20_ac97_codec_write,
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.reset = tegra20_ac97_codec_reset,
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.warm_reset = tegra20_ac97_codec_warm_reset,
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};
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static inline void tegra20_ac97_start_playback(struct tegra20_ac97 *ac97)
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{
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regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
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TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN,
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TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN);
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regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
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TEGRA20_AC97_CTRL_PCM_DAC_EN |
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TEGRA20_AC97_CTRL_STM_EN,
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TEGRA20_AC97_CTRL_PCM_DAC_EN |
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TEGRA20_AC97_CTRL_STM_EN);
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}
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static inline void tegra20_ac97_stop_playback(struct tegra20_ac97 *ac97)
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{
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regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
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TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN, 0);
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regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
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TEGRA20_AC97_CTRL_PCM_DAC_EN, 0);
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}
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static inline void tegra20_ac97_start_capture(struct tegra20_ac97 *ac97)
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{
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regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
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TEGRA20_AC97_FIFO_SCR_REC_FULL_EN,
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TEGRA20_AC97_FIFO_SCR_REC_FULL_EN);
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}
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static inline void tegra20_ac97_stop_capture(struct tegra20_ac97 *ac97)
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{
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regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
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TEGRA20_AC97_FIFO_SCR_REC_FULL_EN, 0);
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}
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static int tegra20_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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case SNDRV_PCM_TRIGGER_RESUME:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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tegra20_ac97_start_playback(ac97);
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else
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tegra20_ac97_start_capture(ac97);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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tegra20_ac97_stop_playback(ac97);
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else
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tegra20_ac97_stop_capture(ac97);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct snd_soc_dai_ops tegra20_ac97_dai_ops = {
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.trigger = tegra20_ac97_trigger,
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};
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static int tegra20_ac97_probe(struct snd_soc_dai *dai)
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{
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struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
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dai->capture_dma_data = &ac97->capture_dma_data;
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dai->playback_dma_data = &ac97->playback_dma_data;
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return 0;
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}
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static struct snd_soc_dai_driver tegra20_ac97_dai = {
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.name = "tegra-ac97-pcm",
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.bus_control = true,
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.probe = tegra20_ac97_probe,
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.playback = {
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.stream_name = "PCM Playback",
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.capture = {
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.stream_name = "PCM Capture",
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.ops = &tegra20_ac97_dai_ops,
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};
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static const struct snd_soc_component_driver tegra20_ac97_component = {
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.name = DRV_NAME,
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};
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static bool tegra20_ac97_wr_rd_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA20_AC97_CTRL:
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case TEGRA20_AC97_CMD:
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case TEGRA20_AC97_STATUS1:
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case TEGRA20_AC97_FIFO1_SCR:
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case TEGRA20_AC97_FIFO_TX1:
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case TEGRA20_AC97_FIFO_RX1:
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return true;
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default:
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break;
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}
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return false;
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}
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static bool tegra20_ac97_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA20_AC97_STATUS1:
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case TEGRA20_AC97_FIFO1_SCR:
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case TEGRA20_AC97_FIFO_TX1:
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case TEGRA20_AC97_FIFO_RX1:
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return true;
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default:
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break;
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}
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return false;
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}
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static bool tegra20_ac97_precious_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA20_AC97_FIFO_TX1:
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case TEGRA20_AC97_FIFO_RX1:
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return true;
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default:
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break;
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}
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return false;
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}
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static const struct regmap_config tegra20_ac97_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = TEGRA20_AC97_FIFO_RX1,
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.writeable_reg = tegra20_ac97_wr_rd_reg,
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.readable_reg = tegra20_ac97_wr_rd_reg,
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.volatile_reg = tegra20_ac97_volatile_reg,
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.precious_reg = tegra20_ac97_precious_reg,
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.cache_type = REGCACHE_FLAT,
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};
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static int tegra20_ac97_platform_probe(struct platform_device *pdev)
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{
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struct tegra20_ac97 *ac97;
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struct resource *mem;
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void __iomem *regs;
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int ret = 0;
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ac97 = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_ac97),
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GFP_KERNEL);
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if (!ac97) {
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ret = -ENOMEM;
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goto err;
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}
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dev_set_drvdata(&pdev->dev, ac97);
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ac97->clk_ac97 = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(ac97->clk_ac97)) {
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dev_err(&pdev->dev, "Can't retrieve ac97 clock\n");
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ret = PTR_ERR(ac97->clk_ac97);
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goto err;
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}
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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regs = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(regs)) {
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ret = PTR_ERR(regs);
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goto err_clk_put;
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}
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ac97->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
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&tegra20_ac97_regmap_config);
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if (IS_ERR(ac97->regmap)) {
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dev_err(&pdev->dev, "regmap init failed\n");
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ret = PTR_ERR(ac97->regmap);
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goto err_clk_put;
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}
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ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node,
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"nvidia,codec-reset-gpio", 0);
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if (gpio_is_valid(ac97->reset_gpio)) {
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ret = devm_gpio_request_one(&pdev->dev, ac97->reset_gpio,
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GPIOF_OUT_INIT_HIGH, "codec-reset");
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if (ret) {
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dev_err(&pdev->dev, "could not get codec-reset GPIO\n");
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goto err_clk_put;
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}
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} else {
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dev_err(&pdev->dev, "no codec-reset GPIO supplied\n");
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goto err_clk_put;
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}
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ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node,
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"nvidia,codec-sync-gpio", 0);
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if (!gpio_is_valid(ac97->sync_gpio)) {
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dev_err(&pdev->dev, "no codec-sync GPIO supplied\n");
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goto err_clk_put;
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}
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ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
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ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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ac97->capture_dma_data.maxburst = 4;
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ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
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ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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ac97->playback_dma_data.maxburst = 4;
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ret = clk_prepare_enable(ac97->clk_ac97);
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if (ret) {
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dev_err(&pdev->dev, "clk_enable failed: %d\n", ret);
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goto err_clk_put;
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}
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ret = snd_soc_set_ac97_ops(&tegra20_ac97_ops);
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if (ret) {
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dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
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goto err_clk_disable_unprepare;
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}
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ret = snd_soc_register_component(&pdev->dev, &tegra20_ac97_component,
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&tegra20_ac97_dai, 1);
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if (ret) {
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dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
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ret = -ENOMEM;
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goto err_clk_disable_unprepare;
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}
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ret = tegra_pcm_platform_register(&pdev->dev);
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if (ret) {
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dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
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goto err_unregister_component;
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}
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/* XXX: crufty ASoC AC97 API - only one AC97 codec allowed */
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workdata = ac97;
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return 0;
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err_unregister_component:
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snd_soc_unregister_component(&pdev->dev);
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err_clk_disable_unprepare:
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clk_disable_unprepare(ac97->clk_ac97);
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err_clk_put:
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err:
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snd_soc_set_ac97_ops(NULL);
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return ret;
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}
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static int tegra20_ac97_platform_remove(struct platform_device *pdev)
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{
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struct tegra20_ac97 *ac97 = dev_get_drvdata(&pdev->dev);
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tegra_pcm_platform_unregister(&pdev->dev);
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snd_soc_unregister_component(&pdev->dev);
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clk_disable_unprepare(ac97->clk_ac97);
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snd_soc_set_ac97_ops(NULL);
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return 0;
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}
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static const struct of_device_id tegra20_ac97_of_match[] = {
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{ .compatible = "nvidia,tegra20-ac97", },
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{},
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};
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static struct platform_driver tegra20_ac97_driver = {
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.driver = {
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.name = DRV_NAME,
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.of_match_table = tegra20_ac97_of_match,
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},
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.probe = tegra20_ac97_platform_probe,
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.remove = tegra20_ac97_platform_remove,
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};
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module_platform_driver(tegra20_ac97_driver);
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MODULE_AUTHOR("Lucas Stach");
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MODULE_DESCRIPTION("Tegra20 AC97 ASoC driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:" DRV_NAME);
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MODULE_DEVICE_TABLE(of, tegra20_ac97_of_match);
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