214 lines
5.7 KiB
C
214 lines
5.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Xilinx XADC driver
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*
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* Copyright 2013 Analog Devices Inc.
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* Author: Lars-Peter Clausen <lars@metafoo.de>
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*/
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#ifndef __IIO_XILINX_XADC__
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#define __IIO_XILINX_XADC__
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#include <linux/interrupt.h>
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#include <linux/mutex.h>
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#include <linux/spinlock.h>
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struct iio_dev;
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struct clk;
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struct xadc_ops;
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struct platform_device;
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void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events);
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int xadc_read_event_config(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan, enum iio_event_type type,
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enum iio_event_direction dir);
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int xadc_write_event_config(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan, enum iio_event_type type,
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enum iio_event_direction dir, int state);
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int xadc_read_event_value(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan, enum iio_event_type type,
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enum iio_event_direction dir, enum iio_event_info info,
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int *val, int *val2);
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int xadc_write_event_value(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan, enum iio_event_type type,
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enum iio_event_direction dir, enum iio_event_info info,
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int val, int val2);
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enum xadc_external_mux_mode {
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XADC_EXTERNAL_MUX_NONE,
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XADC_EXTERNAL_MUX_SINGLE,
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XADC_EXTERNAL_MUX_DUAL,
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};
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struct xadc {
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void __iomem *base;
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struct clk *clk;
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const struct xadc_ops *ops;
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uint16_t threshold[16];
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uint16_t temp_hysteresis;
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unsigned int alarm_mask;
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uint16_t *data;
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struct iio_trigger *trigger;
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struct iio_trigger *convst_trigger;
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struct iio_trigger *samplerate_trigger;
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enum xadc_external_mux_mode external_mux_mode;
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unsigned int zynq_masked_alarm;
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unsigned int zynq_intmask;
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struct delayed_work zynq_unmask_work;
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struct mutex mutex;
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spinlock_t lock;
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struct completion completion;
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int irq;
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};
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enum xadc_type {
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XADC_TYPE_S7, /* Series 7 */
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XADC_TYPE_US, /* UltraScale and UltraScale+ */
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};
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struct xadc_ops {
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int (*read)(struct xadc *xadc, unsigned int reg, uint16_t *val);
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int (*write)(struct xadc *xadc, unsigned int reg, uint16_t val);
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int (*setup)(struct platform_device *pdev, struct iio_dev *indio_dev,
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int irq);
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void (*update_alarm)(struct xadc *xadc, unsigned int alarm);
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unsigned long (*get_dclk_rate)(struct xadc *xadc);
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irqreturn_t (*interrupt_handler)(int irq, void *devid);
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unsigned int flags;
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enum xadc_type type;
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};
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static inline int _xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
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uint16_t *val)
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{
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lockdep_assert_held(&xadc->mutex);
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return xadc->ops->read(xadc, reg, val);
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}
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static inline int _xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
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uint16_t val)
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{
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lockdep_assert_held(&xadc->mutex);
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return xadc->ops->write(xadc, reg, val);
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}
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static inline int xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
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uint16_t *val)
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{
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int ret;
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mutex_lock(&xadc->mutex);
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ret = _xadc_read_adc_reg(xadc, reg, val);
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mutex_unlock(&xadc->mutex);
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return ret;
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}
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static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
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uint16_t val)
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{
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int ret;
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mutex_lock(&xadc->mutex);
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ret = _xadc_write_adc_reg(xadc, reg, val);
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mutex_unlock(&xadc->mutex);
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return ret;
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}
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/* XADC hardmacro register definitions */
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#define XADC_REG_TEMP 0x00
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#define XADC_REG_VCCINT 0x01
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#define XADC_REG_VCCAUX 0x02
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#define XADC_REG_VPVN 0x03
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#define XADC_REG_VREFP 0x04
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#define XADC_REG_VREFN 0x05
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#define XADC_REG_VCCBRAM 0x06
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#define XADC_REG_VCCPINT 0x0d
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#define XADC_REG_VCCPAUX 0x0e
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#define XADC_REG_VCCO_DDR 0x0f
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#define XADC_REG_VAUX(x) (0x10 + (x))
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#define XADC_REG_MAX_TEMP 0x20
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#define XADC_REG_MAX_VCCINT 0x21
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#define XADC_REG_MAX_VCCAUX 0x22
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#define XADC_REG_MAX_VCCBRAM 0x23
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#define XADC_REG_MIN_TEMP 0x24
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#define XADC_REG_MIN_VCCINT 0x25
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#define XADC_REG_MIN_VCCAUX 0x26
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#define XADC_REG_MIN_VCCBRAM 0x27
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#define XADC_REG_MAX_VCCPINT 0x28
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#define XADC_REG_MAX_VCCPAUX 0x29
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#define XADC_REG_MAX_VCCO_DDR 0x2a
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#define XADC_REG_MIN_VCCPINT 0x2c
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#define XADC_REG_MIN_VCCPAUX 0x2d
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#define XADC_REG_MIN_VCCO_DDR 0x2e
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#define XADC_REG_CONF0 0x40
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#define XADC_REG_CONF1 0x41
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#define XADC_REG_CONF2 0x42
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#define XADC_REG_SEQ(x) (0x48 + (x))
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#define XADC_REG_INPUT_MODE(x) (0x4c + (x))
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#define XADC_REG_THRESHOLD(x) (0x50 + (x))
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#define XADC_REG_FLAG 0x3f
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#define XADC_CONF0_EC BIT(9)
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#define XADC_CONF0_ACQ BIT(8)
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#define XADC_CONF0_MUX BIT(11)
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#define XADC_CONF0_CHAN(x) (x)
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#define XADC_CONF1_SEQ_MASK (0xf << 12)
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#define XADC_CONF1_SEQ_DEFAULT (0 << 12)
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#define XADC_CONF1_SEQ_SINGLE_PASS (1 << 12)
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#define XADC_CONF1_SEQ_CONTINUOUS (2 << 12)
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#define XADC_CONF1_SEQ_SINGLE_CHANNEL (3 << 12)
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#define XADC_CONF1_SEQ_SIMULTANEOUS (4 << 12)
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#define XADC_CONF1_SEQ_INDEPENDENT (8 << 12)
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#define XADC_CONF1_ALARM_MASK 0x0f0f
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#define XADC_CONF2_DIV_MASK 0xff00
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#define XADC_CONF2_DIV_OFFSET 8
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#define XADC_CONF2_PD_MASK (0x3 << 4)
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#define XADC_CONF2_PD_NONE (0x0 << 4)
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#define XADC_CONF2_PD_ADC_B (0x2 << 4)
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#define XADC_CONF2_PD_BOTH (0x3 << 4)
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#define XADC_ALARM_TEMP_MASK BIT(0)
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#define XADC_ALARM_VCCINT_MASK BIT(1)
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#define XADC_ALARM_VCCAUX_MASK BIT(2)
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#define XADC_ALARM_OT_MASK BIT(3)
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#define XADC_ALARM_VCCBRAM_MASK BIT(4)
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#define XADC_ALARM_VCCPINT_MASK BIT(5)
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#define XADC_ALARM_VCCPAUX_MASK BIT(6)
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#define XADC_ALARM_VCCODDR_MASK BIT(7)
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#define XADC_THRESHOLD_TEMP_MAX 0x0
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#define XADC_THRESHOLD_VCCINT_MAX 0x1
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#define XADC_THRESHOLD_VCCAUX_MAX 0x2
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#define XADC_THRESHOLD_OT_MAX 0x3
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#define XADC_THRESHOLD_TEMP_MIN 0x4
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#define XADC_THRESHOLD_VCCINT_MIN 0x5
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#define XADC_THRESHOLD_VCCAUX_MIN 0x6
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#define XADC_THRESHOLD_OT_MIN 0x7
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#define XADC_THRESHOLD_VCCBRAM_MAX 0x8
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#define XADC_THRESHOLD_VCCPINT_MAX 0x9
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#define XADC_THRESHOLD_VCCPAUX_MAX 0xa
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#define XADC_THRESHOLD_VCCODDR_MAX 0xb
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#define XADC_THRESHOLD_VCCBRAM_MIN 0xc
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#define XADC_THRESHOLD_VCCPINT_MIN 0xd
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#define XADC_THRESHOLD_VCCPAUX_MIN 0xe
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#define XADC_THRESHOLD_VCCODDR_MIN 0xf
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#endif
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