484 lines
16 KiB
Plaintext
484 lines
16 KiB
Plaintext
Semantics and Behavior of Atomic and
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Bitmask Operations
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David S. Miller
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This document is intended to serve as a guide to Linux port
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maintainers on how to implement atomic counter, bitops, and spinlock
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interfaces properly.
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The atomic_t type should be defined as a signed integer.
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Also, it should be made opaque such that any kind of cast to a normal
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C integer type will fail. Something like the following should
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suffice:
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typedef struct { volatile int counter; } atomic_t;
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The first operations to implement for atomic_t's are the
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initializers and plain reads.
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#define ATOMIC_INIT(i) { (i) }
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#define atomic_set(v, i) ((v)->counter = (i))
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The first macro is used in definitions, such as:
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static atomic_t my_counter = ATOMIC_INIT(1);
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The second interface can be used at runtime, as in:
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struct foo { atomic_t counter; };
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...
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struct foo *k;
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k = kmalloc(sizeof(*k), GFP_KERNEL);
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if (!k)
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return -ENOMEM;
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atomic_set(&k->counter, 0);
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Next, we have:
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#define atomic_read(v) ((v)->counter)
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which simply reads the current value of the counter.
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Now, we move onto the actual atomic operation interfaces.
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void atomic_add(int i, atomic_t *v);
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void atomic_sub(int i, atomic_t *v);
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void atomic_inc(atomic_t *v);
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void atomic_dec(atomic_t *v);
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These four routines add and subtract integral values to/from the given
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atomic_t value. The first two routines pass explicit integers by
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which to make the adjustment, whereas the latter two use an implicit
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adjustment value of "1".
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One very important aspect of these two routines is that they DO NOT
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require any explicit memory barriers. They need only perform the
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atomic_t counter update in an SMP safe manner.
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Next, we have:
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int atomic_inc_return(atomic_t *v);
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int atomic_dec_return(atomic_t *v);
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These routines add 1 and subtract 1, respectively, from the given
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atomic_t and return the new counter value after the operation is
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performed.
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Unlike the above routines, it is required that explicit memory
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barriers are performed before and after the operation. It must be
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done such that all memory operations before and after the atomic
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operation calls are strongly ordered with respect to the atomic
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operation itself.
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For example, it should behave as if a smp_mb() call existed both
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before and after the atomic operation.
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If the atomic instructions used in an implementation provide explicit
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memory barrier semantics which satisfy the above requirements, that is
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fine as well.
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Let's move on:
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int atomic_add_return(int i, atomic_t *v);
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int atomic_sub_return(int i, atomic_t *v);
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These behave just like atomic_{inc,dec}_return() except that an
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explicit counter adjustment is given instead of the implicit "1".
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This means that like atomic_{inc,dec}_return(), the memory barrier
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semantics are required.
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Next:
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int atomic_inc_and_test(atomic_t *v);
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int atomic_dec_and_test(atomic_t *v);
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These two routines increment and decrement by 1, respectively, the
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given atomic counter. They return a boolean indicating whether the
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resulting counter value was zero or not.
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It requires explicit memory barrier semantics around the operation as
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above.
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int atomic_sub_and_test(int i, atomic_t *v);
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This is identical to atomic_dec_and_test() except that an explicit
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decrement is given instead of the implicit "1". It requires explicit
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memory barrier semantics around the operation.
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int atomic_add_negative(int i, atomic_t *v);
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The given increment is added to the given atomic counter value. A
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boolean is return which indicates whether the resulting counter value
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is negative. It requires explicit memory barrier semantics around the
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operation.
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Then:
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int atomic_cmpxchg(atomic_t *v, int old, int new);
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This performs an atomic compare exchange operation on the atomic value v,
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with the given old and new values. Like all atomic_xxx operations,
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atomic_cmpxchg will only satisfy its atomicity semantics as long as all
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other accesses of *v are performed through atomic_xxx operations.
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atomic_cmpxchg requires explicit memory barriers around the operation.
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The semantics for atomic_cmpxchg are the same as those defined for 'cas'
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below.
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Finally:
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int atomic_add_unless(atomic_t *v, int a, int u);
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If the atomic value v is not equal to u, this function adds a to v, and
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returns non zero. If v is equal to u then it returns zero. This is done as
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an atomic operation.
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atomic_add_unless requires explicit memory barriers around the operation.
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atomic_inc_not_zero, equivalent to atomic_add_unless(v, 1, 0)
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If a caller requires memory barrier semantics around an atomic_t
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operation which does not return a value, a set of interfaces are
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defined which accomplish this:
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void smp_mb__before_atomic_dec(void);
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void smp_mb__after_atomic_dec(void);
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void smp_mb__before_atomic_inc(void);
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void smp_mb__after_atomic_inc(void);
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For example, smp_mb__before_atomic_dec() can be used like so:
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obj->dead = 1;
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smp_mb__before_atomic_dec();
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atomic_dec(&obj->ref_count);
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It makes sure that all memory operations preceding the atomic_dec()
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call are strongly ordered with respect to the atomic counter
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operation. In the above example, it guarantees that the assignment of
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"1" to obj->dead will be globally visible to other cpus before the
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atomic counter decrement.
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Without the explicit smp_mb__before_atomic_dec() call, the
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implementation could legally allow the atomic counter update visible
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to other cpus before the "obj->dead = 1;" assignment.
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The other three interfaces listed are used to provide explicit
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ordering with respect to memory operations after an atomic_dec() call
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(smp_mb__after_atomic_dec()) and around atomic_inc() calls
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(smp_mb__{before,after}_atomic_inc()).
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A missing memory barrier in the cases where they are required by the
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atomic_t implementation above can have disastrous results. Here is
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an example, which follows a pattern occurring frequently in the Linux
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kernel. It is the use of atomic counters to implement reference
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counting, and it works such that once the counter falls to zero it can
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be guaranteed that no other entity can be accessing the object:
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static void obj_list_add(struct obj *obj)
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{
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obj->active = 1;
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list_add(&obj->list);
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}
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static void obj_list_del(struct obj *obj)
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{
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list_del(&obj->list);
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obj->active = 0;
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}
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static void obj_destroy(struct obj *obj)
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{
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BUG_ON(obj->active);
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kfree(obj);
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}
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struct obj *obj_list_peek(struct list_head *head)
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{
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if (!list_empty(head)) {
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struct obj *obj;
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obj = list_entry(head->next, struct obj, list);
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atomic_inc(&obj->refcnt);
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return obj;
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}
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return NULL;
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}
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void obj_poke(void)
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{
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struct obj *obj;
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spin_lock(&global_list_lock);
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obj = obj_list_peek(&global_list);
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spin_unlock(&global_list_lock);
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if (obj) {
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obj->ops->poke(obj);
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if (atomic_dec_and_test(&obj->refcnt))
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obj_destroy(obj);
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}
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}
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void obj_timeout(struct obj *obj)
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{
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spin_lock(&global_list_lock);
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obj_list_del(obj);
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spin_unlock(&global_list_lock);
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if (atomic_dec_and_test(&obj->refcnt))
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obj_destroy(obj);
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}
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(This is a simplification of the ARP queue management in the
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generic neighbour discover code of the networking. Olaf Kirch
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found a bug wrt. memory barriers in kfree_skb() that exposed
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the atomic_t memory barrier requirements quite clearly.)
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Given the above scheme, it must be the case that the obj->active
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update done by the obj list deletion be visible to other processors
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before the atomic counter decrement is performed.
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Otherwise, the counter could fall to zero, yet obj->active would still
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be set, thus triggering the assertion in obj_destroy(). The error
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sequence looks like this:
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cpu 0 cpu 1
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obj_poke() obj_timeout()
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obj = obj_list_peek();
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... gains ref to obj, refcnt=2
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obj_list_del(obj);
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obj->active = 0 ...
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... visibility delayed ...
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atomic_dec_and_test()
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... refcnt drops to 1 ...
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atomic_dec_and_test()
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... refcount drops to 0 ...
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obj_destroy()
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BUG() triggers since obj->active
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still seen as one
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obj->active update visibility occurs
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With the memory barrier semantics required of the atomic_t operations
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which return values, the above sequence of memory visibility can never
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happen. Specifically, in the above case the atomic_dec_and_test()
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counter decrement would not become globally visible until the
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obj->active update does.
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As a historical note, 32-bit Sparc used to only allow usage of
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24-bits of it's atomic_t type. This was because it used 8 bits
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as a spinlock for SMP safety. Sparc32 lacked a "compare and swap"
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type instruction. However, 32-bit Sparc has since been moved over
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to a "hash table of spinlocks" scheme, that allows the full 32-bit
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counter to be realized. Essentially, an array of spinlocks are
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indexed into based upon the address of the atomic_t being operated
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on, and that lock protects the atomic operation. Parisc uses the
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same scheme.
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Another note is that the atomic_t operations returning values are
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extremely slow on an old 386.
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We will now cover the atomic bitmask operations. You will find that
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their SMP and memory barrier semantics are similar in shape and scope
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to the atomic_t ops above.
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Native atomic bit operations are defined to operate on objects aligned
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to the size of an "unsigned long" C data type, and are least of that
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size. The endianness of the bits within each "unsigned long" are the
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native endianness of the cpu.
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void set_bit(unsigned long nr, volatile unsigned long *addr);
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void clear_bit(unsigned long nr, volatile unsigned long *addr);
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void change_bit(unsigned long nr, volatile unsigned long *addr);
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These routines set, clear, and change, respectively, the bit number
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indicated by "nr" on the bit mask pointed to by "ADDR".
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They must execute atomically, yet there are no implicit memory barrier
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semantics required of these interfaces.
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int test_and_set_bit(unsigned long nr, volatile unsigned long *addr);
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int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);
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int test_and_change_bit(unsigned long nr, volatile unsigned long *addr);
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Like the above, except that these routines return a boolean which
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indicates whether the changed bit was set _BEFORE_ the atomic bit
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operation.
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WARNING! It is incredibly important that the value be a boolean,
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ie. "0" or "1". Do not try to be fancy and save a few instructions by
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declaring the above to return "long" and just returning something like
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"old_val & mask" because that will not work.
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For one thing, this return value gets truncated to int in many code
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paths using these interfaces, so on 64-bit if the bit is set in the
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upper 32-bits then testers will never see that.
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One great example of where this problem crops up are the thread_info
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flag operations. Routines such as test_and_set_ti_thread_flag() chop
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the return value into an int. There are other places where things
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like this occur as well.
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These routines, like the atomic_t counter operations returning values,
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require explicit memory barrier semantics around their execution. All
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memory operations before the atomic bit operation call must be made
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visible globally before the atomic bit operation is made visible.
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Likewise, the atomic bit operation must be visible globally before any
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subsequent memory operation is made visible. For example:
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obj->dead = 1;
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if (test_and_set_bit(0, &obj->flags))
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/* ... */;
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obj->killed = 1;
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The implementation of test_and_set_bit() must guarantee that
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"obj->dead = 1;" is visible to cpus before the atomic memory operation
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done by test_and_set_bit() becomes visible. Likewise, the atomic
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memory operation done by test_and_set_bit() must become visible before
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"obj->killed = 1;" is visible.
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Finally there is the basic operation:
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int test_bit(unsigned long nr, __const__ volatile unsigned long *addr);
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Which returns a boolean indicating if bit "nr" is set in the bitmask
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pointed to by "addr".
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If explicit memory barriers are required around clear_bit() (which
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does not return a value, and thus does not need to provide memory
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barrier semantics), two interfaces are provided:
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void smp_mb__before_clear_bit(void);
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void smp_mb__after_clear_bit(void);
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They are used as follows, and are akin to their atomic_t operation
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brothers:
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/* All memory operations before this call will
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* be globally visible before the clear_bit().
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*/
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smp_mb__before_clear_bit();
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clear_bit( ... );
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/* The clear_bit() will be visible before all
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* subsequent memory operations.
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*/
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smp_mb__after_clear_bit();
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Finally, there are non-atomic versions of the bitmask operations
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provided. They are used in contexts where some other higher-level SMP
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locking scheme is being used to protect the bitmask, and thus less
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expensive non-atomic operations may be used in the implementation.
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They have names similar to the above bitmask operation interfaces,
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except that two underscores are prefixed to the interface name.
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void __set_bit(unsigned long nr, volatile unsigned long *addr);
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void __clear_bit(unsigned long nr, volatile unsigned long *addr);
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void __change_bit(unsigned long nr, volatile unsigned long *addr);
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int __test_and_set_bit(unsigned long nr, volatile unsigned long *addr);
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int __test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);
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int __test_and_change_bit(unsigned long nr, volatile unsigned long *addr);
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These non-atomic variants also do not require any special memory
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barrier semantics.
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The routines xchg() and cmpxchg() need the same exact memory barriers
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as the atomic and bit operations returning values.
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Spinlocks and rwlocks have memory barrier expectations as well.
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The rule to follow is simple:
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1) When acquiring a lock, the implementation must make it globally
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visible before any subsequent memory operation.
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2) When releasing a lock, the implementation must make it such that
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all previous memory operations are globally visible before the
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lock release.
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Which finally brings us to _atomic_dec_and_lock(). There is an
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architecture-neutral version implemented in lib/dec_and_lock.c,
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but most platforms will wish to optimize this in assembler.
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int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock);
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Atomically decrement the given counter, and if will drop to zero
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atomically acquire the given spinlock and perform the decrement
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of the counter to zero. If it does not drop to zero, do nothing
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with the spinlock.
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It is actually pretty simple to get the memory barrier correct.
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Simply satisfy the spinlock grab requirements, which is make
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sure the spinlock operation is globally visible before any
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subsequent memory operation.
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We can demonstrate this operation more clearly if we define
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an abstract atomic operation:
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long cas(long *mem, long old, long new);
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"cas" stands for "compare and swap". It atomically:
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1) Compares "old" with the value currently at "mem".
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2) If they are equal, "new" is written to "mem".
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3) Regardless, the current value at "mem" is returned.
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As an example usage, here is what an atomic counter update
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might look like:
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void example_atomic_inc(long *counter)
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{
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long old, new, ret;
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while (1) {
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old = *counter;
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new = old + 1;
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ret = cas(counter, old, new);
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if (ret == old)
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break;
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}
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}
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Let's use cas() in order to build a pseudo-C atomic_dec_and_lock():
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int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock)
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{
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long old, new, ret;
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int went_to_zero;
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went_to_zero = 0;
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while (1) {
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old = atomic_read(atomic);
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new = old - 1;
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if (new == 0) {
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went_to_zero = 1;
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spin_lock(lock);
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}
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ret = cas(atomic, old, new);
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if (ret == old)
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break;
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if (went_to_zero) {
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spin_unlock(lock);
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went_to_zero = 0;
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}
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}
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return went_to_zero;
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}
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Now, as far as memory barriers go, as long as spin_lock()
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strictly orders all subsequent memory operations (including
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the cas()) with respect to itself, things will be fine.
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Said another way, _atomic_dec_and_lock() must guarantee that
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a counter dropping to zero is never made visible before the
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spinlock being acquired.
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Note that this also means that for the case where the counter
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is not dropping to zero, there are no memory ordering
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requirements.
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