54 lines
1.7 KiB
Plaintext
54 lines
1.7 KiB
Plaintext
* Cadence NAND controller
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Required properties:
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- compatible : "cdns,hp-nfc"
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- reg : Contains two entries, each of which is a tuple consisting of a
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physical address and length. The first entry is the address and
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length of the controller register set. The second entry is the
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address and length of the Slave DMA data port.
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- reg-names: should contain "reg" and "sdma"
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- #address-cells: should be 1. The cell encodes the chip select connection.
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- #size-cells : should be 0.
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- interrupts : The interrupt number.
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- clocks: phandle of the controller core clock (nf_clk).
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Optional properties:
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- dmas: shall reference DMA channel associated to the NAND controller
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- cdns,board-delay-ps : Estimated Board delay. The value includes the total
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round trip delay for the signals and is used for deciding on values
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associated with data read capture. The example formula for SDR mode is
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the following:
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board delay = RE#PAD delay + PCB trace to device + PCB trace from device
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+ DQ PAD delay
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Child nodes represent the available NAND chips.
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Required properties of NAND chips:
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- reg: shall contain the native Chip Select ids from 0 to max supported by
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the cadence nand flash controller
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See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
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generic bindings.
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Example:
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nand_controller: nand-controller@60000000 {
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compatible = "cdns,hp-nfc";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
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reg-names = "reg", "sdma";
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clocks = <&nf_clk>;
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cdns,board-delay-ps = <4830>;
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interrupts = <2 0>;
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nand@0 {
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reg = <0>;
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label = "nand-1";
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};
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nand@1 {
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reg = <1>;
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label = "nand-2";
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};
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};
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