601 lines
14 KiB
C
601 lines
14 KiB
C
/*
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* Copyright 2015 IBM Corp.
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*
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* Joel Stanley <joel@jms.id.au>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/gpio/driver.h>
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#include <linux/pinctrl/consumer.h>
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struct aspeed_bank_props {
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unsigned int bank;
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u32 input;
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u32 output;
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};
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struct aspeed_gpio_config {
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unsigned int nr_gpios;
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const struct aspeed_bank_props *props;
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};
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struct aspeed_gpio {
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struct gpio_chip chip;
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spinlock_t lock;
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void __iomem *base;
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int irq;
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const struct aspeed_gpio_config *config;
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};
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struct aspeed_gpio_bank {
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uint16_t val_regs;
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uint16_t irq_regs;
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const char names[4][3];
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};
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static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
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{
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.val_regs = 0x0000,
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.irq_regs = 0x0008,
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.names = { "A", "B", "C", "D" },
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},
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{
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.val_regs = 0x0020,
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.irq_regs = 0x0028,
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.names = { "E", "F", "G", "H" },
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},
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{
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.val_regs = 0x0070,
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.irq_regs = 0x0098,
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.names = { "I", "J", "K", "L" },
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},
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{
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.val_regs = 0x0078,
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.irq_regs = 0x00e8,
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.names = { "M", "N", "O", "P" },
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},
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{
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.val_regs = 0x0080,
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.irq_regs = 0x0118,
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.names = { "Q", "R", "S", "T" },
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},
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{
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.val_regs = 0x0088,
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.irq_regs = 0x0148,
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.names = { "U", "V", "W", "X" },
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},
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{
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.val_regs = 0x01E0,
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.irq_regs = 0x0178,
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.names = { "Y", "Z", "AA", "AB" },
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},
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{
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.val_regs = 0x01E8,
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.irq_regs = 0x01A8,
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.names = { "AC", "", "", "" },
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},
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};
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#define GPIO_BANK(x) ((x) >> 5)
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#define GPIO_OFFSET(x) ((x) & 0x1f)
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#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
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#define GPIO_DATA 0x00
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#define GPIO_DIR 0x04
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#define GPIO_IRQ_ENABLE 0x00
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#define GPIO_IRQ_TYPE0 0x04
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#define GPIO_IRQ_TYPE1 0x08
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#define GPIO_IRQ_TYPE2 0x0c
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#define GPIO_IRQ_STATUS 0x10
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static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
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{
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unsigned int bank = GPIO_BANK(offset);
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WARN_ON(bank > ARRAY_SIZE(aspeed_gpio_banks));
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return &aspeed_gpio_banks[bank];
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}
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static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props)
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{
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return !(props->input || props->output);
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}
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static inline const struct aspeed_bank_props *find_bank_props(
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struct aspeed_gpio *gpio, unsigned int offset)
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{
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const struct aspeed_bank_props *props = gpio->config->props;
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while (!is_bank_props_sentinel(props)) {
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if (props->bank == GPIO_BANK(offset))
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return props;
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props++;
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}
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return NULL;
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}
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static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset)
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{
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const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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unsigned int group = GPIO_OFFSET(offset) / 8;
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return bank->names[group][0] != '\0' &&
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(!props || ((props->input | props->output) & GPIO_BIT(offset)));
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}
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static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
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{
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const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
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return !props || (props->input & GPIO_BIT(offset));
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}
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#define have_irq(g, o) have_input((g), (o))
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static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
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{
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const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
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return !props || (props->output & GPIO_BIT(offset));
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}
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static void __iomem *bank_val_reg(struct aspeed_gpio *gpio,
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const struct aspeed_gpio_bank *bank,
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unsigned int reg)
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{
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return gpio->base + bank->val_regs + reg;
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}
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static void __iomem *bank_irq_reg(struct aspeed_gpio *gpio,
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const struct aspeed_gpio_bank *bank,
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unsigned int reg)
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{
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return gpio->base + bank->irq_regs + reg;
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}
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static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset)
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{
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struct aspeed_gpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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return !!(ioread32(bank_val_reg(gpio, bank, GPIO_DATA))
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& GPIO_BIT(offset));
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}
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static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
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int val)
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{
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struct aspeed_gpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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void __iomem *addr;
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u32 reg;
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addr = bank_val_reg(gpio, bank, GPIO_DATA);
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reg = ioread32(addr);
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if (val)
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reg |= GPIO_BIT(offset);
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else
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reg &= ~GPIO_BIT(offset);
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iowrite32(reg, addr);
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}
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static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
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int val)
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{
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struct aspeed_gpio *gpio = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&gpio->lock, flags);
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__aspeed_gpio_set(gc, offset, val);
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spin_unlock_irqrestore(&gpio->lock, flags);
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}
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static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
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{
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struct aspeed_gpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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unsigned long flags;
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u32 reg;
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if (!have_input(gpio, offset))
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return -ENOTSUPP;
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spin_lock_irqsave(&gpio->lock, flags);
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reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR));
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iowrite32(reg & ~GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR));
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spin_unlock_irqrestore(&gpio->lock, flags);
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return 0;
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}
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static int aspeed_gpio_dir_out(struct gpio_chip *gc,
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unsigned int offset, int val)
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{
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struct aspeed_gpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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unsigned long flags;
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u32 reg;
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if (!have_output(gpio, offset))
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return -ENOTSUPP;
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spin_lock_irqsave(&gpio->lock, flags);
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reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR));
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iowrite32(reg | GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR));
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__aspeed_gpio_set(gc, offset, val);
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spin_unlock_irqrestore(&gpio->lock, flags);
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return 0;
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}
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static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
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{
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struct aspeed_gpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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unsigned long flags;
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u32 val;
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if (!have_input(gpio, offset))
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return 0;
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if (!have_output(gpio, offset))
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return 1;
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spin_lock_irqsave(&gpio->lock, flags);
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val = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)) & GPIO_BIT(offset);
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spin_unlock_irqrestore(&gpio->lock, flags);
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return !val;
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}
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static inline int irqd_to_aspeed_gpio_data(struct irq_data *d,
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struct aspeed_gpio **gpio,
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const struct aspeed_gpio_bank **bank,
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u32 *bit)
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{
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int offset;
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struct aspeed_gpio *internal;
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offset = irqd_to_hwirq(d);
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internal = irq_data_get_irq_chip_data(d);
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/* This might be a bit of a questionable place to check */
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if (!have_irq(internal, offset))
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return -ENOTSUPP;
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*gpio = internal;
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*bank = to_bank(offset);
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*bit = GPIO_BIT(offset);
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return 0;
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}
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static void aspeed_gpio_irq_ack(struct irq_data *d)
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{
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const struct aspeed_gpio_bank *bank;
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struct aspeed_gpio *gpio;
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unsigned long flags;
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void __iomem *status_addr;
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u32 bit;
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int rc;
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rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
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if (rc)
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return;
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status_addr = bank_irq_reg(gpio, bank, GPIO_IRQ_STATUS);
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spin_lock_irqsave(&gpio->lock, flags);
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iowrite32(bit, status_addr);
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spin_unlock_irqrestore(&gpio->lock, flags);
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}
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static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
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{
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const struct aspeed_gpio_bank *bank;
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struct aspeed_gpio *gpio;
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unsigned long flags;
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u32 reg, bit;
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void __iomem *addr;
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int rc;
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rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
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if (rc)
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return;
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addr = bank_irq_reg(gpio, bank, GPIO_IRQ_ENABLE);
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spin_lock_irqsave(&gpio->lock, flags);
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reg = ioread32(addr);
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if (set)
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reg |= bit;
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else
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reg &= bit;
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iowrite32(reg, addr);
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spin_unlock_irqrestore(&gpio->lock, flags);
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}
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static void aspeed_gpio_irq_mask(struct irq_data *d)
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{
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aspeed_gpio_irq_set_mask(d, false);
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}
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static void aspeed_gpio_irq_unmask(struct irq_data *d)
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{
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aspeed_gpio_irq_set_mask(d, true);
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}
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static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type)
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{
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u32 type0 = 0;
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u32 type1 = 0;
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u32 type2 = 0;
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u32 bit, reg;
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const struct aspeed_gpio_bank *bank;
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irq_flow_handler_t handler;
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struct aspeed_gpio *gpio;
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unsigned long flags;
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void __iomem *addr;
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int rc;
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rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
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if (rc)
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return -EINVAL;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_BOTH:
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type2 |= bit;
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case IRQ_TYPE_EDGE_RISING:
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type0 |= bit;
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case IRQ_TYPE_EDGE_FALLING:
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handler = handle_edge_irq;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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type0 |= bit;
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case IRQ_TYPE_LEVEL_LOW:
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type1 |= bit;
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handler = handle_level_irq;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&gpio->lock, flags);
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addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE0);
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reg = ioread32(addr);
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reg = (reg & ~bit) | type0;
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iowrite32(reg, addr);
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addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE1);
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reg = ioread32(addr);
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reg = (reg & ~bit) | type1;
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iowrite32(reg, addr);
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addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE2);
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reg = ioread32(addr);
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reg = (reg & ~bit) | type2;
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iowrite32(reg, addr);
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spin_unlock_irqrestore(&gpio->lock, flags);
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irq_set_handler_locked(d, handler);
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return 0;
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}
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static void aspeed_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct irq_chip *ic = irq_desc_get_chip(desc);
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struct aspeed_gpio *data = gpiochip_get_data(gc);
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unsigned int i, p, girq;
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unsigned long reg;
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chained_irq_enter(ic, desc);
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for (i = 0; i < ARRAY_SIZE(aspeed_gpio_banks); i++) {
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const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
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reg = ioread32(bank_irq_reg(data, bank, GPIO_IRQ_STATUS));
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for_each_set_bit(p, ®, 32) {
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girq = irq_find_mapping(gc->irqdomain, i * 32 + p);
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generic_handle_irq(girq);
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}
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}
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chained_irq_exit(ic, desc);
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}
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static struct irq_chip aspeed_gpio_irqchip = {
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.name = "aspeed-gpio",
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.irq_ack = aspeed_gpio_irq_ack,
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.irq_mask = aspeed_gpio_irq_mask,
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.irq_unmask = aspeed_gpio_irq_unmask,
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.irq_set_type = aspeed_gpio_set_type,
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};
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static void set_irq_valid_mask(struct aspeed_gpio *gpio)
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{
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const struct aspeed_bank_props *props = gpio->config->props;
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while (!is_bank_props_sentinel(props)) {
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unsigned int offset;
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const unsigned long int input = props->input;
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/* Pretty crummy approach, but similar to GPIO core */
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for_each_clear_bit(offset, &input, 32) {
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unsigned int i = props->bank * 32 + offset;
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if (i >= gpio->config->nr_gpios)
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break;
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clear_bit(i, gpio->chip.irq_valid_mask);
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}
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props++;
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}
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}
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static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio,
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struct platform_device *pdev)
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{
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int rc;
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rc = platform_get_irq(pdev, 0);
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if (rc < 0)
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return rc;
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gpio->irq = rc;
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set_irq_valid_mask(gpio);
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rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_gpio_irqchip,
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0, handle_bad_irq, IRQ_TYPE_NONE);
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if (rc) {
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dev_info(&pdev->dev, "Could not add irqchip\n");
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return rc;
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}
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gpiochip_set_chained_irqchip(&gpio->chip, &aspeed_gpio_irqchip,
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gpio->irq, aspeed_gpio_irq_handler);
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return 0;
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}
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static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset)
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{
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if (!have_gpio(gpiochip_get_data(chip), offset))
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return -ENODEV;
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return pinctrl_request_gpio(chip->base + offset);
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}
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static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
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{
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pinctrl_free_gpio(chip->base + offset);
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}
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/*
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* Any banks not specified in a struct aspeed_bank_props array are assumed to
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* have the properties:
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*
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* { .input = 0xffffffff, .output = 0xffffffff }
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*/
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static const struct aspeed_bank_props ast2400_bank_props[] = {
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/* input output */
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{ 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
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{ 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
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{ },
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};
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static const struct aspeed_gpio_config ast2400_config =
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/* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
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{ .nr_gpios = 220, .props = ast2400_bank_props, };
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static const struct aspeed_bank_props ast2500_bank_props[] = {
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/* input output */
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{ 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
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{ 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
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{ 7, 0x000000ff, 0x000000ff }, /* AC */
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{ },
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};
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static const struct aspeed_gpio_config ast2500_config =
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/* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
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{ .nr_gpios = 232, .props = ast2500_bank_props, };
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static const struct of_device_id aspeed_gpio_of_table[] = {
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{ .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
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{ .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
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{}
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};
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MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table);
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static int __init aspeed_gpio_probe(struct platform_device *pdev)
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{
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const struct of_device_id *gpio_id;
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struct aspeed_gpio *gpio;
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struct resource *res;
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int rc;
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gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
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if (!gpio)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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gpio->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(gpio->base))
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return PTR_ERR(gpio->base);
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spin_lock_init(&gpio->lock);
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gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node);
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if (!gpio_id)
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return -EINVAL;
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gpio->config = gpio_id->data;
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gpio->chip.ngpio = gpio->config->nr_gpios;
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gpio->chip.parent = &pdev->dev;
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gpio->chip.direction_input = aspeed_gpio_dir_in;
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gpio->chip.direction_output = aspeed_gpio_dir_out;
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gpio->chip.get_direction = aspeed_gpio_get_direction;
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gpio->chip.request = aspeed_gpio_request;
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gpio->chip.free = aspeed_gpio_free;
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gpio->chip.get = aspeed_gpio_get;
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gpio->chip.set = aspeed_gpio_set;
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gpio->chip.label = dev_name(&pdev->dev);
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gpio->chip.base = -1;
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gpio->chip.irq_need_valid_mask = true;
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rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
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if (rc < 0)
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return rc;
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return aspeed_gpio_setup_irqs(gpio, pdev);
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}
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static struct platform_driver aspeed_gpio_driver = {
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = aspeed_gpio_of_table,
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},
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};
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module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe);
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MODULE_DESCRIPTION("Aspeed GPIO Driver");
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MODULE_LICENSE("GPL");
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