Andi Kleen 03195c6b40 x86, mce, cmci: define MSR names and fields for new CMCI registers ... Impact: New register definitions only CMCI means support for raising an interrupt on a corrected machine check event instead of having to poll for it. It's a new feature in Intel Nehalem CPUs available on some machine check banks. For details see the IA32 SDM Vol3a 14.5 Define the registers for it as a preparation for further patches. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>		2009-02-24 13:41:00 -08:00
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asm	x86, mce, cmci: define MSR names and fields for new CMCI registers	2009-02-24 13:41:00 -08:00