171 lines
5.9 KiB
C
171 lines
5.9 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU7_H
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#define SMU7_H
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#pragma pack(push, 1)
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#define SMU7_CONTEXT_ID_SMC 1
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#define SMU7_CONTEXT_ID_VBIOS 2
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#define SMU7_CONTEXT_ID_SMC 1
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#define SMU7_CONTEXT_ID_VBIOS 2
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#define SMU7_MAX_LEVELS_VDDC 8
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#define SMU7_MAX_LEVELS_VDDCI 4
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#define SMU7_MAX_LEVELS_MVDD 4
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#define SMU7_MAX_LEVELS_VDDNB 8
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#define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
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#define SMU7_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM
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#define SMU7_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels
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#define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes.
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#define SMU7_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD.
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#define SMU7_MAX_LEVELS_VCE 8 // ECLK levels for VCE.
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#define SMU7_MAX_LEVELS_ACP 8 // ACLK levels for ACP.
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#define SMU7_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU.
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#define SMU7_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table.
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#define DPM_NO_LIMIT 0
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#define DPM_NO_UP 1
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#define DPM_GO_DOWN 2
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#define DPM_GO_UP 3
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#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
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#define SMU7_FIRST_DPM_MEMORY_LEVEL 0
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#define GPIO_CLAMP_MODE_VRHOT 1
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#define GPIO_CLAMP_MODE_THERM 2
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#define GPIO_CLAMP_MODE_DC 4
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#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
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#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
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#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
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#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
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#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6
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#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
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#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9
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#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
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#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12
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#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
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#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15
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#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
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#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18
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#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
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#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21
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#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
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#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
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#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
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#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
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#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
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struct SMU7_PIDController
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{
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uint32_t Ki;
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int32_t LFWindupUL;
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int32_t LFWindupLL;
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uint32_t StatePrecision;
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uint32_t LfPrecision;
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uint32_t LfOffset;
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uint32_t MaxState;
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uint32_t MaxLfFraction;
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uint32_t StateShift;
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};
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typedef struct SMU7_PIDController SMU7_PIDController;
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// -------------------------------------------------------------------------------------------------------------------------
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#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
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#define SMU7_SCLK_DPM_CONFIG_MASK 0x01
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#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
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#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
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#define SMU7_MCLK_DPM_CONFIG_MASK 0x08
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#define SMU7_UVD_DPM_CONFIG_MASK 0x10
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#define SMU7_VCE_DPM_CONFIG_MASK 0x20
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#define SMU7_ACP_DPM_CONFIG_MASK 0x40
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#define SMU7_SAMU_DPM_CONFIG_MASK 0x80
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#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
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#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
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#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
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#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
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#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
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#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
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#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
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struct SMU7_Firmware_Header
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{
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uint32_t Digest[5];
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uint32_t Version;
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uint32_t HeaderSize;
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uint32_t Flags;
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uint32_t EntryPoint;
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uint32_t CodeSize;
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uint32_t ImageSize;
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uint32_t Rtos;
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uint32_t SoftRegisters;
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uint32_t DpmTable;
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uint32_t FanTable;
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uint32_t CacConfigTable;
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uint32_t CacStatusTable;
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uint32_t mcRegisterTable;
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uint32_t mcArbDramTimingTable;
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uint32_t PmFuseTable;
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uint32_t Globals;
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uint32_t Reserved[42];
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uint32_t Signature;
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};
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typedef struct SMU7_Firmware_Header SMU7_Firmware_Header;
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#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
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enum DisplayConfig {
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PowerDown = 1,
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DP54x4,
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DP54x2,
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DP54x1,
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DP27x4,
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DP27x2,
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DP27x1,
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HDMI297,
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HDMI162,
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LVDS,
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DP324x4,
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DP324x2,
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DP324x1
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};
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#pragma pack(pop)
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#endif
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