253 lines
6.0 KiB
C
253 lines
6.0 KiB
C
/*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/reset.h>
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#include <linux/regulator/consumer.h>
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#include <linux/iommu.h>
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#include <soc/tegra/fuse.h>
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#include <soc/tegra/pmc.h>
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#include "nouveau_drm.h"
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#include "nouveau_platform.h"
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static int nouveau_platform_power_up(struct nouveau_platform_gpu *gpu)
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{
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int err;
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err = regulator_enable(gpu->vdd);
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if (err)
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goto err_power;
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err = clk_prepare_enable(gpu->clk);
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if (err)
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goto err_clk;
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err = clk_prepare_enable(gpu->clk_pwr);
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if (err)
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goto err_clk_pwr;
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clk_set_rate(gpu->clk_pwr, 204000000);
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udelay(10);
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reset_control_assert(gpu->rst);
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udelay(10);
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err = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D);
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if (err)
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goto err_clamp;
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udelay(10);
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reset_control_deassert(gpu->rst);
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udelay(10);
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return 0;
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err_clamp:
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clk_disable_unprepare(gpu->clk_pwr);
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err_clk_pwr:
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clk_disable_unprepare(gpu->clk);
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err_clk:
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regulator_disable(gpu->vdd);
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err_power:
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return err;
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}
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static int nouveau_platform_power_down(struct nouveau_platform_gpu *gpu)
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{
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int err;
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reset_control_assert(gpu->rst);
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udelay(10);
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clk_disable_unprepare(gpu->clk_pwr);
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clk_disable_unprepare(gpu->clk);
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udelay(10);
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err = regulator_disable(gpu->vdd);
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if (err)
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return err;
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return 0;
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}
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static void nouveau_platform_probe_iommu(struct device *dev,
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struct nouveau_platform_gpu *gpu)
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{
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int err;
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unsigned long pgsize_bitmap;
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mutex_init(&gpu->iommu.mutex);
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if (iommu_present(&platform_bus_type)) {
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gpu->iommu.domain = iommu_domain_alloc(&platform_bus_type);
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if (IS_ERR(gpu->iommu.domain))
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goto error;
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/*
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* A IOMMU is only usable if it supports page sizes smaller
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* or equal to the system's PAGE_SIZE, with a preference if
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* both are equal.
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*/
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pgsize_bitmap = gpu->iommu.domain->ops->pgsize_bitmap;
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if (pgsize_bitmap & PAGE_SIZE) {
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gpu->iommu.pgshift = PAGE_SHIFT;
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} else {
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gpu->iommu.pgshift = fls(pgsize_bitmap & ~PAGE_MASK);
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if (gpu->iommu.pgshift == 0) {
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dev_warn(dev, "unsupported IOMMU page size\n");
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goto free_domain;
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}
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gpu->iommu.pgshift -= 1;
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}
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err = iommu_attach_device(gpu->iommu.domain, dev);
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if (err)
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goto free_domain;
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err = nvkm_mm_init(&gpu->iommu._mm, 0,
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(1ULL << 40) >> gpu->iommu.pgshift, 1);
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if (err)
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goto detach_device;
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gpu->iommu.mm = &gpu->iommu._mm;
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}
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return;
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detach_device:
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iommu_detach_device(gpu->iommu.domain, dev);
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free_domain:
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iommu_domain_free(gpu->iommu.domain);
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error:
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gpu->iommu.domain = NULL;
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gpu->iommu.pgshift = 0;
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dev_err(dev, "cannot initialize IOMMU MM\n");
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}
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static void nouveau_platform_remove_iommu(struct device *dev,
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struct nouveau_platform_gpu *gpu)
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{
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if (gpu->iommu.domain) {
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nvkm_mm_fini(&gpu->iommu._mm);
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iommu_detach_device(gpu->iommu.domain, dev);
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iommu_domain_free(gpu->iommu.domain);
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}
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}
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static int nouveau_platform_probe(struct platform_device *pdev)
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{
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struct nouveau_platform_gpu *gpu;
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struct nouveau_platform_device *device;
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struct drm_device *drm;
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int err;
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gpu = devm_kzalloc(&pdev->dev, sizeof(*gpu), GFP_KERNEL);
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if (!gpu)
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return -ENOMEM;
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gpu->vdd = devm_regulator_get(&pdev->dev, "vdd");
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if (IS_ERR(gpu->vdd))
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return PTR_ERR(gpu->vdd);
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gpu->rst = devm_reset_control_get(&pdev->dev, "gpu");
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if (IS_ERR(gpu->rst))
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return PTR_ERR(gpu->rst);
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gpu->clk = devm_clk_get(&pdev->dev, "gpu");
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if (IS_ERR(gpu->clk))
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return PTR_ERR(gpu->clk);
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gpu->clk_pwr = devm_clk_get(&pdev->dev, "pwr");
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if (IS_ERR(gpu->clk_pwr))
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return PTR_ERR(gpu->clk_pwr);
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nouveau_platform_probe_iommu(&pdev->dev, gpu);
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err = nouveau_platform_power_up(gpu);
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if (err)
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return err;
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drm = nouveau_platform_device_create(pdev, &device);
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if (IS_ERR(drm)) {
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err = PTR_ERR(drm);
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goto power_down;
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}
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device->gpu = gpu;
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device->gpu_speedo = tegra_sku_info.gpu_speedo_value;
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err = drm_dev_register(drm, 0);
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if (err < 0)
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goto err_unref;
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return 0;
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err_unref:
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drm_dev_unref(drm);
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power_down:
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nouveau_platform_power_down(gpu);
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nouveau_platform_remove_iommu(&pdev->dev, gpu);
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return err;
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}
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static int nouveau_platform_remove(struct platform_device *pdev)
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{
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struct drm_device *drm_dev = platform_get_drvdata(pdev);
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struct nouveau_drm *drm = nouveau_drm(drm_dev);
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struct nvkm_device *device = nvxx_device(&drm->device);
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struct nouveau_platform_gpu *gpu = nv_device_to_platform(device)->gpu;
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int err;
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nouveau_drm_device_remove(drm_dev);
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err = nouveau_platform_power_down(gpu);
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nouveau_platform_remove_iommu(&pdev->dev, gpu);
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return err;
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}
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#if IS_ENABLED(CONFIG_OF)
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static const struct of_device_id nouveau_platform_match[] = {
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{ .compatible = "nvidia,gk20a" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, nouveau_platform_match);
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#endif
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struct platform_driver nouveau_platform_driver = {
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.driver = {
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.name = "nouveau",
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.of_match_table = of_match_ptr(nouveau_platform_match),
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},
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.probe = nouveau_platform_probe,
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.remove = nouveau_platform_remove,
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};
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