119 lines
3.5 KiB
C
119 lines
3.5 KiB
C
/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Keith Packard <keithp@keithp.com>
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*
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*/
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#if WATCH_LISTS
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int
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i915_verify_lists(struct drm_device *dev)
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{
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static int warned;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj;
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int err = 0;
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if (warned)
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return 0;
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list_for_each_entry(obj, &dev_priv->render_ring.active_list, list) {
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if (obj->base.dev != dev ||
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!atomic_read(&obj->base.refcount.refcount)) {
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DRM_ERROR("freed render active %p\n", obj);
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err++;
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break;
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} else if (!obj->active ||
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(obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) {
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DRM_ERROR("invalid render active %p (a %d r %x)\n",
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obj,
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obj->active,
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obj->base.read_domains);
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err++;
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} else if (obj->base.write_domain && list_empty(&obj->gpu_write_list)) {
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DRM_ERROR("invalid render active %p (w %x, gwl %d)\n",
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obj,
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obj->base.write_domain,
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!list_empty(&obj->gpu_write_list));
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err++;
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}
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}
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list_for_each_entry(obj, &dev_priv->mm.flushing_list, list) {
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if (obj->base.dev != dev ||
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!atomic_read(&obj->base.refcount.refcount)) {
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DRM_ERROR("freed flushing %p\n", obj);
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err++;
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break;
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} else if (!obj->active ||
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(obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0 ||
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list_empty(&obj->gpu_write_list)) {
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DRM_ERROR("invalid flushing %p (a %d w %x gwl %d)\n",
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obj,
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obj->active,
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obj->base.write_domain,
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!list_empty(&obj->gpu_write_list));
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err++;
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}
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}
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list_for_each_entry(obj, &dev_priv->mm.gpu_write_list, gpu_write_list) {
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if (obj->base.dev != dev ||
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!atomic_read(&obj->base.refcount.refcount)) {
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DRM_ERROR("freed gpu write %p\n", obj);
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err++;
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break;
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} else if (!obj->active ||
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(obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) {
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DRM_ERROR("invalid gpu write %p (a %d w %x)\n",
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obj,
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obj->active,
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obj->base.write_domain);
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err++;
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}
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}
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list_for_each_entry(obj, &i915_gtt_vm->inactive_list, list) {
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if (obj->base.dev != dev ||
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!atomic_read(&obj->base.refcount.refcount)) {
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DRM_ERROR("freed inactive %p\n", obj);
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err++;
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break;
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} else if (obj->pin_count || obj->active ||
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(obj->base.write_domain & I915_GEM_GPU_DOMAINS)) {
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DRM_ERROR("invalid inactive %p (p %d a %d w %x)\n",
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obj,
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obj->pin_count, obj->active,
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obj->base.write_domain);
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err++;
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}
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}
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return warned = err;
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}
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#endif /* WATCH_LIST */
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