227 lines
6.0 KiB
C
227 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* Apple SoC Watchdog driver
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*
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* Copyright (C) The Asahi Linux Contributors
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*/
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/limits.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/watchdog.h>
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/*
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* Apple Watchdog MMIO registers
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*
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* This HW block has three separate watchdogs. WD0 resets the machine
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* to recovery mode and is not very useful for us. WD1 and WD2 trigger a normal
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* machine reset. WD0 additionally supports a configurable interrupt.
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* This information can be used to implement pretimeout support at a later time.
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*
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* APPLE_WDT_WDx_CUR_TIME is a simple counter incremented for each tick of the
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* reference clock. It can also be overwritten to any value.
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* Whenever APPLE_WDT_CTRL_RESET_EN is set in APPLE_WDT_WDx_CTRL and
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* APPLE_WDT_WDx_CUR_TIME >= APPLE_WDT_WDx_BITE_TIME the entire machine is
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* reset.
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* Whenever APPLE_WDT_CTRL_IRQ_EN is set and APPLE_WDTx_WD1_CUR_TIME >=
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* APPLE_WDTx_WD1_BARK_TIME an interrupt is triggered and
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* APPLE_WDT_CTRL_IRQ_STATUS is set. The interrupt can be cleared by writing
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* 1 to APPLE_WDT_CTRL_IRQ_STATUS.
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*/
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#define APPLE_WDT_WD0_CUR_TIME 0x00
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#define APPLE_WDT_WD0_BITE_TIME 0x04
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#define APPLE_WDT_WD0_BARK_TIME 0x08
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#define APPLE_WDT_WD0_CTRL 0x0c
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#define APPLE_WDT_WD1_CUR_TIME 0x10
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#define APPLE_WDT_WD1_BITE_TIME 0x14
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#define APPLE_WDT_WD1_CTRL 0x1c
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#define APPLE_WDT_WD2_CUR_TIME 0x20
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#define APPLE_WDT_WD2_BITE_TIME 0x24
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#define APPLE_WDT_WD2_CTRL 0x2c
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#define APPLE_WDT_CTRL_IRQ_EN BIT(0)
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#define APPLE_WDT_CTRL_IRQ_STATUS BIT(1)
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#define APPLE_WDT_CTRL_RESET_EN BIT(2)
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#define APPLE_WDT_TIMEOUT_DEFAULT 30
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struct apple_wdt {
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struct watchdog_device wdd;
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void __iomem *regs;
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unsigned long clk_rate;
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};
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static struct apple_wdt *to_apple_wdt(struct watchdog_device *wdd)
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{
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return container_of(wdd, struct apple_wdt, wdd);
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}
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static int apple_wdt_start(struct watchdog_device *wdd)
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{
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struct apple_wdt *wdt = to_apple_wdt(wdd);
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writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
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writel_relaxed(APPLE_WDT_CTRL_RESET_EN, wdt->regs + APPLE_WDT_WD1_CTRL);
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return 0;
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}
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static int apple_wdt_stop(struct watchdog_device *wdd)
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{
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struct apple_wdt *wdt = to_apple_wdt(wdd);
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writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CTRL);
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return 0;
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}
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static int apple_wdt_ping(struct watchdog_device *wdd)
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{
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struct apple_wdt *wdt = to_apple_wdt(wdd);
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writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
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return 0;
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}
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static int apple_wdt_set_timeout(struct watchdog_device *wdd, unsigned int s)
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{
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struct apple_wdt *wdt = to_apple_wdt(wdd);
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writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
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writel_relaxed(wdt->clk_rate * s, wdt->regs + APPLE_WDT_WD1_BITE_TIME);
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wdd->timeout = s;
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return 0;
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}
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static unsigned int apple_wdt_get_timeleft(struct watchdog_device *wdd)
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{
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struct apple_wdt *wdt = to_apple_wdt(wdd);
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u32 cur_time, reset_time;
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cur_time = readl_relaxed(wdt->regs + APPLE_WDT_WD1_CUR_TIME);
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reset_time = readl_relaxed(wdt->regs + APPLE_WDT_WD1_BITE_TIME);
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return (reset_time - cur_time) / wdt->clk_rate;
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}
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static int apple_wdt_restart(struct watchdog_device *wdd, unsigned long mode,
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void *cmd)
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{
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struct apple_wdt *wdt = to_apple_wdt(wdd);
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writel_relaxed(APPLE_WDT_CTRL_RESET_EN, wdt->regs + APPLE_WDT_WD1_CTRL);
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writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_BITE_TIME);
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writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
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/*
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* Flush writes and then wait for the SoC to reset. Even though the
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* reset is queued almost immediately experiments have shown that it
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* can take up to ~20-25ms until the SoC is actually reset. Just wait
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* 50ms here to be safe.
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*/
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(void)readl_relaxed(wdt->regs + APPLE_WDT_WD1_CUR_TIME);
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mdelay(50);
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return 0;
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}
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static void apple_wdt_clk_disable_unprepare(void *data)
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{
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clk_disable_unprepare(data);
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}
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static struct watchdog_ops apple_wdt_ops = {
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.owner = THIS_MODULE,
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.start = apple_wdt_start,
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.stop = apple_wdt_stop,
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.ping = apple_wdt_ping,
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.set_timeout = apple_wdt_set_timeout,
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.get_timeleft = apple_wdt_get_timeleft,
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.restart = apple_wdt_restart,
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};
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static struct watchdog_info apple_wdt_info = {
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.identity = "Apple SoC Watchdog",
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.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
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};
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static int apple_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct apple_wdt *wdt;
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struct clk *clk;
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u32 wdt_ctrl;
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int ret;
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wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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wdt->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(wdt->regs))
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return PTR_ERR(wdt->regs);
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clk = devm_clk_get(dev, NULL);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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ret = clk_prepare_enable(clk);
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if (ret)
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return ret;
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ret = devm_add_action_or_reset(dev, apple_wdt_clk_disable_unprepare,
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clk);
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if (ret)
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return ret;
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wdt->clk_rate = clk_get_rate(clk);
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if (!wdt->clk_rate)
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return -EINVAL;
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wdt->wdd.ops = &apple_wdt_ops;
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wdt->wdd.info = &apple_wdt_info;
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wdt->wdd.max_timeout = U32_MAX / wdt->clk_rate;
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wdt->wdd.timeout = APPLE_WDT_TIMEOUT_DEFAULT;
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wdt_ctrl = readl_relaxed(wdt->regs + APPLE_WDT_WD1_CTRL);
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if (wdt_ctrl & APPLE_WDT_CTRL_RESET_EN)
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set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
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watchdog_init_timeout(&wdt->wdd, 0, dev);
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apple_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
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watchdog_stop_on_unregister(&wdt->wdd);
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watchdog_set_restart_priority(&wdt->wdd, 128);
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return devm_watchdog_register_device(dev, &wdt->wdd);
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}
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static const struct of_device_id apple_wdt_of_match[] = {
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{ .compatible = "apple,wdt" },
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{},
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};
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MODULE_DEVICE_TABLE(of, apple_wdt_of_match);
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static struct platform_driver apple_wdt_driver = {
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.driver = {
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.name = "apple-watchdog",
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.of_match_table = apple_wdt_of_match,
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},
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.probe = apple_wdt_probe,
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};
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module_platform_driver(apple_wdt_driver);
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MODULE_DESCRIPTION("Apple SoC watchdog driver");
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MODULE_AUTHOR("Sven Peter <sven@svenpeter.dev>");
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MODULE_LICENSE("Dual MIT/GPL");
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