Commit Graph

15 Commits

Author SHA1 Message Date
Ezequiel Garcia 8c2c8c03cd spi: img-spfi: Control CS lines with GPIO
When the CONTINUE bit is set, the interrupt status we are polling to
identify if a transaction has finished can be sporadic.  Even though
the transfer has finished, the interrupt status may erroneously
indicate that there is still data in the FIFO.  This behaviour causes
random timeouts in large PIO transfers.

Instead of using the CONTINUE bit to control the CS lines, use the SPI
core's CS GPIO handling.  Also, now that the CONTINUE bit is not being
used, we can poll for the ALLDONE interrupt to indicate transfer
completion.

Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-08 21:04:51 +01:00
Mark Brown a25202b04f Merge branch 'fix/img-spfi' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-img-spfi 2015-04-08 21:04:43 +01:00
Andrew Bresticker ba33d8ac0c spi: img-spfi: Reset controller after each message
Imagination has recommended that the SPFI controller be reset after
each message, regardless of success or failure.  Do this in an
unprepare_message() callback.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-08 21:04:28 +01:00
Ezequiel Garcia 824ab37df0 spi: img-spfi: Implement a handle_err() callback
The driver can be greatly simplified by moving the transfer timeout
handling to a handle_err() callback.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-08 21:04:28 +01:00
Mark Brown 89cda06d7f Linux 4.0-rc7
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Merge tag 'v4.0-rc7' into spi-img-spfi

Linux 4.0-rc7
2015-04-08 21:04:25 +01:00
Sifan Naeem ede8342bf6 spi: img-spfi: Setup TRANSACTION register before CONTROL register
Setting the transfer length in the TRANSACTION register after the
CONTROL register is programmed causes intermittent timeout issues in
SPFI transfers when using the SPI framework to control the CS GPIO
lines.  To avoid this issue, set transfer length before programming
the CONTROL register.

Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-08 11:35:54 +01:00
Andrew Bresticker 8543d0e72d spi: img-spfi: Limit bit clock to 1/4th of input clock
Although the SPFI BITCLK divider supports a value of up to 255, only
values up to 128 are usable.  This results in a maximum possible bit
clock rate of 1/4th the input clock rate.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-07 12:19:10 +01:00
Ezequiel Garcia b6fe39770a spi: img-spfi: Implement a prepare_message() callback
In preparation for switching to using the SPI core's CS GPIO handling,
move setup of the PORT_STATE register, which must be configured before
CS is asserted, to a prepare_message() callback.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-07 12:17:54 +01:00
Sifan Naeem 6e0050ec8e spi: img-spfi: Remove udelay in soft reset
Removing the udelay between setting and clearing the soft reset bit in
the spfi control register as it is not required.

Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-03 14:27:01 +00:00
Sifan Naeem f165ed6337 spi: img-spfi: Verify max spfi transfer length
Maximum transfer length supported by SPFI is 65535, this is limited
by the number of bits available in SPFI TSize register to represent
the transfer size.
For transfer requests larger than the maximum supported the driver
will return an invalid argument error.

Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-03 14:26:34 +00:00
Andrew Bresticker 549858ce76 spi: img-spfi: Select FIFO based on transfer length
Since the 32-bit FIFO is deeper (64 bytes) than the 8-bit FIFO (16 bytes),
use the 32-bit FIFO when there are at least 32 bits remaining to be
transferred in PIO mode or when the transfer length is 32-bit aligned
in DMA mode.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-24 12:20:22 +00:00
Andrew Bresticker 76fe5e95fa spi: img-spfi: Increase DMA burst size
A 1-byte burst size is rather inefficient and has been shown to cause
TX issues during testing.  Increase the DMA burst size to 4-bytes for
both RX and TX DMA when using the 8-bit FIFO.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-24 12:20:03 +00:00
Andrew Bresticker c0e7dc21d3 spi: img-spfi: Enable controller before starting TX DMA
It is recommended that the SPFI controller be enabled (i.e. setting
SPFI_EN in SPFI_CONTROL) before TX DMA begins.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-22 17:52:07 +00:00
Rafael J. Wysocki 47164fdb3b spi: Replace CONFIG_PM_RUNTIME with CONFIG_PM
A couple of new CONFIG_PM_RUNTIME users have been added recently
in the SPI subsystem.

However, after commit b2b49ccbdd (PM: Kconfig: Set PM_RUNTIME if
PM_SLEEP is selected) PM_RUNTIME is always set if PM is set, so
#ifdef blocks depending on CONFIG_PM_RUNTIME may now be changed to
depend on CONFIG_PM.

Replace CONFIG_PM_RUNTIME with CONFIG_PM everywhere under
drivers/spi/ (again).

Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Mark Brown <broonie@kernel.org>
2014-12-19 15:25:31 +01:00
Andrew Bresticker deba25800a spi: Add driver for IMG SPFI controller
Add support for the Synchronous Peripheral Flash Interface (SPFI) master
controller found on IMG SoCs.  The SPFI controller supports 5 chip-select
lines and single/dual/quad mode SPI transfers.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-11-17 13:31:08 +00:00