Commit Graph

293 Commits

Author SHA1 Message Date
Alex Deucher 9b1be4dc02 drm/radeon: fix UVD on big endian
This fixes the kernel side so that the ring should come
up and ring and IB tests should work.  The userspace
UVD drivers will also need big endian fixes.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-12 08:17:21 -04:00
Samuel Li 65337e60a7 drm/radeon: Use direct mapping for fast fb access on RS780/RS880 (v2)
v2: fix trailing whitespace

Signed-off-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-03 10:36:21 -04:00
Adis Hamzić e49f3959a9 radeon: Fix system hang issue when using KMS with older cards
The current radeon driver initialization routines, when using KMS, are written
so that the IRQ installation routine is called before initializing the WB buffer
and the CP rings. With some ASICs, though, the IRQ routine tries to access the
GFX_INDEX ring causing a call to RREG32 with the value of -1 in
radeon_fence_read. This, in turn causes the system to completely hang with some
cards, requiring a hard reset.

A call stack that can cause such a hang looks like this (using rv515 ASIC for the
example here):
 * rv515_init (rv515.c)
 * radeon_irq_kms_init (radeon_irq_kms.c)
 * drm_irq_install (drm_irq.c)
 * radeon_driver_irq_preinstall_kms (radeon_irq_kms.c)
 * rs600_irq_process (rs600.c)
 * radeon_fence_process - due to SW interrupt (radeon_fence.c)
 * radeon_fence_read (radeon_fence.c)
 * hang due to RREG32(-1)

The patch moves the IRQ installation to the card startup routine, after the ring
has been initialized, but before the IRQ has been set. This fixes the issue, but
requires a check to see if the IRQ is already installed, as is the case in the
system resume codepath.
I have tested the patch on three machines using the rv515, the rv770 and the
evergreen ASIC. They worked without issues.

This seems to be a known issue and has been reported on several bug tracking
sites by various distributions (see links below). Most of reports recommend
booting the system with KMS disabled and then enabling KMS by reloading the
radeon module. For some reason, this was indeed a usable workaround, however,
UMS is now deprecated and disabled by default.

Bug reports:
https://bugzilla.redhat.com/show_bug.cgi?id=845745
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/561789
https://bbs.archlinux.org/viewtopic.php?id=156964

Signed-off-by: Adis Hamzić <adis@hamzadis.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-06-03 10:17:54 -04:00
Kleber Sacilotto de Souza 7e0e419637 radeon: use max_bus_speed to activate gen2 speeds
radeon currently uses a drm function to get the speed capabilities for
the bus, drm_pcie_get_speed_cap_mask. However, this is a non-standard
method of performing this detection and this patch changes it to use
the max_bus_speed attribute.

From: Lucas Kannebley Tavares <lucaskt@linux.vnet.ibm.com>
Signed-off-by: Kleber Sacilotto de Souza <klebers@linux.vnet.ibm.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-29 12:36:12 -04:00
Christian König 03708b0529 drm/radeon: disable UVD advanced semaphore mode
Not needed and seems to cause some problems.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-23 18:04:01 -04:00
Christian König b05e9e4c9d drm/radeon: raise UVD clocks on init v3
v2: not only raise the clocks on VCPU boot, but also on IB test.
v3: agd5f: fix r600_uvd_init return value.

fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=63730

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-23 18:03:51 -04:00
Alex Deucher d5445a17e7 drm/radeon: update r600 set/get pcie lane config
Updated to the preferred programming sequence.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09 10:31:41 -04:00
Alex Deucher 492d2b61b3 drm/radeon/kms: replace *REG32_PCIE_P with *REG32_PCIE_PORT
Avoid confusion with the *REG32_P mask macro.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09 10:31:40 -04:00
Christian König f2ba57b5ea drm/radeon: UVD bringup v8
Just everything needed to decode videos using UVD.

v6: just all the bugfixes and support for R7xx-SI merged in one patch
v7: UVD_CGC_GATE is a write only register, lockup detection fix
v8: split out VRAM fallback changes, remove support for RV770,
    add support for HEMLOCK, add buffer sizes checks

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09 10:31:33 -04:00
Alex Deucher 9ed8b1f93c drm/radeon: clean up vram/gtt location handling
Add a per-asic MC (memory controller) mask which holds the
mak address mask the asic is capable of.  Use this when
calculating the vram and gtt locations rather using asic
specific functions or limiting everything to 32 bits.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09 10:23:50 -04:00
Alex Deucher d808fc8829 drm/radeon: skip MC reset as it's probably not hung
The MC is mostly likely busy (e.g., display requests), not hung
so no need to reset it.  Doing an MC reset is tricky and not
particularly reliable.  Fixes hangs in certain cases.

Reported-by: Josh Boyer <jwboyer@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-03-07 12:58:58 -05:00
Alex Deucher d041889414 drm/radeon: switch get_gpu_clock() to a callback (v2)
Cleans up the code for future asics

v2: rebase, fix some missing radeon_asic updates

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-02-20 08:51:21 -05:00
Alex Deucher 454d2e2a32 drm/radeon: add a asic callback to get the xclk
This is required to get the reference clock used
by the gfx engine for things like timestamps. Fixes
support for GL extensions the use timestamps on
certain boards.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-02-20 08:51:20 -05:00
Alex Deucher 24178ec42b drm/radeon: don't reset the MC on IGPs/APUs
The MC isn't part of the GPU per se.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:58 -05:00
Alex Deucher 123bc1832c drm/radeon: use the reset mask to determine if rings are hung
fetch the reset mask and check if the relevant ring flags
are set to determine whether the ring is hung or not.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:57 -05:00
Alex Deucher ca57802e52 drm/radeon: halt engines before disabling MC (6xx/7xx)
It's better to halt the engines before we disable the MC.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:55 -05:00
Alex Deucher f13f7731a2 drm/radeon: use status regs to determine what to reset (6xx/7xx)
When we attempt the reset the GPU, look at the status registers
to determine what blocks need to be reset.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:52 -05:00
Alex Deucher d3cb781e83 drm/radeon: rework GPU reset on r6xx/r7xx
Update the code to better match the recommended
programming sequence for soft reset.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:49 -05:00
Alex Deucher 410a3418a8 drm/radeon: add a bios scratch asic hung helper
Used by all asic families from r600+.
Flag for the vbios and later instances of the driver
that the GPU is hung.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:49 -05:00
Mikko Tiihonen f689e3acbd drm/radeon: protect against div by 0 in backend setup
Make sure at least one RB is enabled in
r6xx_remap_render_backend() to avoid an division by
zero in some corner cases.

See:
https://bugzilla.redhat.com/show_bug.cgi?id=892233

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-01-30 14:10:04 -05:00
Michel Dänzer b3dfcb207e drm/radeon: Enable DMA_IB_SWAP_ENABLE on big endian hosts.
Fixes GPU hang during DMA ring IB test.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59672

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-24 14:00:22 -05:00
Alex Deucher 19fc42ed99 drm/radeon: clear reset flags if engines are idle
Fixes a hard lock in the gpu reset code after the
rework for DMA support (0ecebb9e0d
"drm/radeon: switch to a finer grained reset for evergreen")
due to not bailing before the MC shutdown if the relevant engines
are idle.

Discussion:
http://lists.freedesktop.org/archives/dri-devel/2013-January/032985.html

Reported-by: Eldad Zack <eldad@fogrefinery.com>
Tested-by: Eldad Zack <eldad@fogrefinery.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-15 09:06:38 -05:00
Alex Deucher 43fb778754 drm/radeon: split r6xx and r7xx copy_dma functions
- r6xx actually uses a slightly different packet format,
although both formats seem to work ok.
- r7xx doesn't have the count multiple of 2 limitation.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-04 09:29:54 -05:00
Alex Deucher 71e3d1578c drm/radeon: switch to a finer grained reset for r6xx/7xx
No change in functionality as we currently set all the reset
flags.

Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-03 21:28:24 -05:00
Jerome Glisse 64c56e8ce3 drm/radeon: reset dma engine on gpu reset (v2)
This try to reset the dma engine when performing gpu reset. Hopefully
bringing back the gpu dma engine in sane state.

v2: agd5f: fix dma reset on cayman/TN, add support for SI

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-03 13:18:41 -05:00
Jerome Glisse eaaa6983ab drm/radeon: print dma status reg on lockup (v2)
To help debug dma related lockup.

v2: agd5f: update SI as well

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-03 13:18:41 -05:00
Alex Deucher 909d9eb67f drm/radeon/r6xx: fix DMA engine for ttm bo transfers
count must be a multiple of 2. Fixes crashes on
R6xx chips reported by a number of people.

Cc: Borislav Petkov <bp@alien8.de>
Cc: Markus Trippelsdorf <markus@trippelsdorf.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Tested-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-03 13:17:31 -05:00
Jerome Glisse 86a1881d08 drm/radeon: fix fence driver for dma ring when wb is disabled
The dma ring can't write to register thus have to write to memory
its fence value. This ensure that it doesn't try to use scratch
register for dma ring fence driver.

Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=58166

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-12-12 17:16:51 -05:00
Dave Airlie a636a98291 Merge branch 'drm-next-3.8' of git://people.freedesktop.org/~agd5f/linux into drm-next
Alex writes:
"adds support for the
asynchronous DMA engines on r6xx-SI.  These engines are used
for ttm bo moves and VM page table updates currently.  They
could also be exposed via the CS ioctl for userspace use,
but I haven't had a chance to add proper CS checker patches
for them yet.  These patches have been tested extensively
internally for months, so they should be pretty solid."

* 'drm-next-3.8' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: use DMA engine for VM page table updates on SI
  drm/radeon: add dma engine support for vm pt updates on si (v2)
  drm/radeon: use DMA engine for VM page table updates on cayman/TN
  drm/radeon: add dma engine support for vm pt updates on ni (v5)
  drm/radeon: use async dma for ttm buffer moves on 6xx-SI
  drm/radeon/kms: add support for dma rings to radeon_test_moves()
  drm/radeon/kms: Add initial support for async DMA on SI
  drm/radeon/kms: Add initial support for async DMA on cayman/TN
  drm/radeon/kms: Add initial support for async DMA on evergreen
  drm/radeon/kms: Add initial support for async DMA on r6xx/r7xx
2012-12-11 08:46:03 +10:00
Alex Deucher 4d75658bff drm/radeon/kms: Add initial support for async DMA on r6xx/r7xx
Uses the new multi-ring infrastucture.  6xx/7xx has a single
async DMA ring.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-12-10 16:53:23 -05:00
Akinobu Mita ef8cf3a1c5 drm/radeon: Use hweight32
Use hweight32 instead of counting for each bit

Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: David Airlie <airlied@linux.ie>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-11-20 16:06:18 +10:00
Alex Deucher 3691feea98 drm/radeon: check if pcie gen 2 is already enabled (v2)
If so, skip enabling it to save time.

v2: coding style fixes

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-15 13:21:02 -04:00
Linus Torvalds 612a9aab56 Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull drm merge (part 1) from Dave Airlie:
 "So first of all my tree and uapi stuff has a conflict mess, its my
  fault as the nouveau stuff didn't hit -next as were trying to rebase
  regressions out of it before we merged.

  Highlights:
   - SH mobile modesetting driver and associated helpers
   - some DRM core documentation
   - i915 modesetting rework, haswell hdmi, haswell and vlv fixes, write
     combined pte writing, ilk rc6 support,
   - nouveau: major driver rework into a hw core driver, makes features
     like SLI a lot saner to implement,
   - psb: add eDP/DP support for Cedarview
   - radeon: 2 layer page tables, async VM pte updates, better PLL
     selection for > 2 screens, better ACPI interactions

  The rest is general grab bag of fixes.

  So why part 1? well I have the exynos pull req which came in a bit
  late but was waiting for me to do something they shouldn't have and it
  looks fairly safe, and David Howells has some more header cleanups
  he'd like me to pull, that seem like a good idea, but I'd like to get
  this merge out of the way so -next dosen't get blocked."

Tons of conflicts mostly due to silly include line changes, but mostly
mindless.  A few other small semantic conflicts too, noted from Dave's
pre-merged branch.

* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (447 commits)
  drm/nv98/crypt: fix fuc build with latest envyas
  drm/nouveau/devinit: fixup various issues with subdev ctor/init ordering
  drm/nv41/vm: fix and enable use of "real" pciegart
  drm/nv44/vm: fix and enable use of "real" pciegart
  drm/nv04/dmaobj: fixup vm target handling in preparation for nv4x pcie
  drm/nouveau: store supported dma mask in vmmgr
  drm/nvc0/ibus: initial implementation of subdev
  drm/nouveau/therm: add support for fan-control modes
  drm/nouveau/hwmon: rename pwm0* to pmw1* to follow hwmon's rules
  drm/nouveau/therm: calculate the pwm divisor on nv50+
  drm/nouveau/fan: rewrite the fan tachometer driver to get more precision, faster
  drm/nouveau/therm: move thermal-related functions to the therm subdev
  drm/nouveau/bios: parse the pwm divisor from the perf table
  drm/nouveau/therm: use the EXTDEV table to detect i2c monitoring devices
  drm/nouveau/therm: rework thermal table parsing
  drm/nouveau/gpio: expose the PWM/TOGGLE parameter found in the gpio vbios table
  drm/nouveau: fix pm initialization order
  drm/nouveau/bios: check that fixed tvdac gpio data is valid before using it
  drm/nouveau: log channel debug/error messages from client object rather than drm client
  drm/nouveau: have drm debugging macros build on top of core macros
  ...
2012-10-03 23:29:23 -07:00
David Howells 760285e7e7 UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
Convert #include "..." to #include <path/...> in drivers/gpu/.

Signed-off-by: David Howells <dhowells@redhat.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Acked-by: Dave Jones <davej@redhat.com>
2012-10-02 18:01:07 +01:00
Michel Dänzer af026c5bd1 drm/radeon: Fix scratch register leak in IB test.
Restructure the code to jump out via labels instead of directly returning
early. Also make error reporting consistent across all hardware generations.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Simon Kitching <skitching@vonos.net>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27 10:22:42 -04:00
Lauri Kasanen 1109ca09b9 drm/radeon: Mark all possible functions / structs as static
Let's allow GCC to optimize better.

This exposed some five unused functions, but this patch doesn't remove them.

Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20 13:10:41 -04:00
Christian König 4bf3dd9264 drm/radeon: cleanup VM id handling a bit
Store a reference to the VM into the IB structure, that
makes calculating the IBs address a bit less complicated.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20 13:10:38 -04:00
Alex Deucher ee93b86be1 drm/radeon: remove gui_idle interrupt infrastructure
It was only used for dynpm, but has been replaced with
a better implementation using fences.  Remove it.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20 13:10:33 -04:00
Marek Olšák 6759a0a7a0 drm/radeon/kms: implement timestamp userspace query (v2)
Returns a snapshot of the GPU clock counter.  Needed
for certain OpenGL extensions.

v2: agd5f
- address Jerome's comments
- add function documentation

Signed-off-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-13 10:50:56 -04:00
Dave Airlie 197bbb3d46 drm/radeon/kms: auto detect pcie link speed from root port
This check the root ports supported link speeds and enables
GEN2 mode if the 5.0 GT link speed is available.

The first 3.0 cards are SI so they will probably need more investigation.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-07-19 22:30:32 -04:00
Jerome Glisse 440a7cd87e drm/radeon: improve GPU lockup debugging info on r6xx/r7xx/r8xx/r9xx
Print various CP register that have valuable informations regarding
GPU lockup.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-07-19 22:28:07 -04:00
Alex Deucher 89d35807fb drm/radeon: update rptr saving logic for memory buffers
Add support for using memory buffers rather than
scratch registers.  Some rings may not be able to
write to scratch registers.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-07-18 13:53:17 +02:00
Alex Deucher 8b25ed3482 drm/radeon: remove radeon_ring_index()
Just store the index in the ring structure.
Idea taken from one of Jerome's wip rptr patches.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-07-18 13:33:54 +02:00
Christian König 4ef72566f1 drm/radeon: fix const IB handling v2
Const IBs are executed on the CE not the CP, so we can't
fence them in the normal way.

So submit them directly before the IB instead, just as
the documentation says.

v2: keep the extra documentation

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-18 13:17:49 +02:00
Christian König 45df68035c drm/radeon: record what is next valid wptr for each ring v4
Before emitting any indirect buffer, emit the offset of the next
valid ring content if any. This allow code that want to resume
ring to resume ring right after ib that caused GPU lockup.

v2: use scratch registers instead of storing it into memory
v3: skip over the surface sync for ni and si as well
v4: use SET_CONFIG_REG instead of PACKET0

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-17 10:33:09 +02:00
Christian König 04eb2206d8 drm/radeon: move radeon_ib_ring_tests out of chipset code
Making it easier to control when it is executed.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-17 10:33:01 +02:00
Christian König 6f72a63199 drm/radeon: remove r600_blit_suspend
Just reinitialize the shader content on resume instead.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-17 10:32:48 +02:00
Christian König 2898c348e5 drm/radeon: remove ip_pool start/suspend
The IB pool is in gart memory, so it is completely
superfluous to unpin / repin it on suspend / resume.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-17 10:32:41 +02:00
Christian König d40fd3a337 drm/radeon: remove FIXME comment from chipset suspend
For a normal suspend/resume we allready wait for
the rings to be empty, and for a suspend/reasume
in case of a lockup we REALLY don't want to wait
for anything.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-17 10:32:28 +02:00
Christian Koenig 736fc37fd7 drm/radeon: replace pflip and sw_int counters with atomics
So we can skip the locking. Also renames sw_int to
ring_int, cause that better matches its purpose.

Signed-off-by: Christian Koenig <christian.koenig@amd.com>
2012-06-21 09:38:53 +02:00