Commit Graph

7 Commits

Author SHA1 Message Date
Max Filippov 5bb8def55d xtensa: support ioremap for memory outside KIO region
Map physical memory outside KIO region into the vmalloc area.
Unmap it with vunmap.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-01-11 17:37:36 +03:00
Max Filippov b6cee17b7d xtensa: nommu: don't build most of the cache flushing code
Most cache flushing code is only relevant for MMU. Don't build it for
nommu configuration.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-10-21 13:28:50 +04:00
Max Filippov 6555910065 xtensa: add HIGHMEM support
Introduce fixmap area just below the vmalloc region. Use it for atomic
mapping of high memory pages.
High memory on cores with cache aliasing is not supported and is still
to be implemented. Fail build for such configurations for now.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-04-06 21:29:21 +04:00
Johannes Weiner e5083a63b6 xtensa: nommu support
Add support for !CONFIG_MMU setups.

Signed-off-by: Johannes Weiner <jw@emlix.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2009-04-02 23:41:50 -07:00
Adrian Bunk d3883ecebb Remove references to "make dep"
"make dep" is no longer required in kernel 2.6, but was still mentioned
in some places.

Signed-off-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2008-01-28 23:22:13 +01:00
Chris Zankel 6656920b0b [XTENSA] Add support for cache-aliasing
Add support for processors that have cache-aliasing issues, such as
the Stretch S5000 processor. Cache-aliasing means that the size of
the cache (for one way) is larger than the page size, thus, a page
can end up in several places in cache depending on the virtual to
physical translation. The method used here is to map a user page
temporarily through the auto-refill way 0 and of of the DTLB.
We probably will want to revisit this issue and use a better
approach with kmap/kunmap.

Signed-off-by: Chris Zankel <chris@zankel.net>
2007-08-27 13:54:16 -07:00
Chris Zankel 3f65ce4d14 [PATCH] xtensa: Architecture support for Tensilica Xtensa Part 5
The attached patches provides part 5 of an architecture implementation for the
Tensilica Xtensa CPU series.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-24 00:05:22 -07:00