Commit Graph

6 Commits

Author SHA1 Message Date
Annaliese McDermond a23e34c064
ASoC: tlv320aic32x4: Fix potential uninitialized variable
Fix compiler warning about uninitialized variable reported by
Stephen Rothwell <sfr@canb.auug.org.au>.

Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-02 10:46:19 +09:00
Annaliese McDermond daae4c5835
ASoC: tlv320aic32x4: Fix spacing
Fix some cosmetic spacing issues reported by Julia Lawall
<julia.lawall@lip6.fr>.

Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-08 14:16:49 +07:00
Annaliese McDermond 9b484124eb
ASoC: tlv320aic32x4: Model BDIV divider in CCF
Model and manage BDIV divider as components in the Core
Clock Framework.  This should allow us to do some more complex
clock management and power control.  Also, some of the
on-board chip clocks can be exposed to the outside, and this
change will make those clocks easier to consume by other
parts of the kernel.

Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-25 15:54:01 +00:00
Annaliese McDermond a51b500620
ASoC: tlv320aic32x4: Model DAC/ADC dividers in CCF
Model and manage DAC/ADC dividers as components in the Core
Clock Framework.  This should allow us to do some more complex
clock management and power control.  Also, some of the
on-board chip clocks can be exposed to the outside, and this
change will make those clocks easier to consume by other
parts of the kernel.

Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-25 15:53:47 +00:00
Annaliese McDermond fd2df3aeaf
ASoC: tlv320aic32x4: Model CODEC_CLKIN in CCF
Model and manage codec clock input as a component in the Core
Clock Framework.  This should allow us to do some more complex
clock management and power control.  Also, some of the
on-board chip clocks can be exposed to the outside, and this
change will make those clocks easier to consume by other
parts of the kernel.

Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-25 15:53:33 +00:00
Annaliese McDermond 514b044cba
ASoC: tlv320aic32x4: Model PLL in CCF
Model and manage the on-board PLL as a component in the Core
Clock Framework.  This should allow us to do some more complex
clock management and power control.  Also, some of the
on-board chip clocks can be exposed to the outside, and this
change will make those clocks easier to consume by other
parts of the kernel.

Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-25 15:53:19 +00:00