Add hook so that the HW RNG source on the TS-78xx is available.
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Received official word finally from Technological Systems on which
FPGA ID's they have released unto the world. Also an additional of
a dummy entry matching the FPGA ID of the Verilog template on our
wiki.
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Stefan Agner found his board comes with 0x00b480/0x02 but the main
board also has Rev B printed on it like my 0x00b480/0x03. Some light
enum renaming was needed but it was to be expected.
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Added checks to the platform_device_(register|add) calls so that if
a device failed to load it would then not later be unloaded; also
added the hooks so that it would not try to unload when the RTC
driver support is compiled out.
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
Signed-off-by: Nicolas Pitre <nico@cam.org>
the FPGA on the TS-7800 provides access to a number of devices
and so we have to be careful when reprogramming it. As we
are effectively turning a bus off/on we have to inform the
kernel that it should stop using anything provided by the
FPGA (currently only the RTC however the NAND, LCD, etc is
to come) before it's reprogrammed.
Once reprogramed, we can tell the kernel to (re)enable things
by checking the FPGA ID against a lookup table for what a
particular FPGA bitstream can provide.
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
The TS-7800's M25P40 is not available to the kernel, it's used
to load the initial bitstream onto the FPGA and so these hooks
point to nothing and need to be removed.
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
Currently, there are two different fields in the
mv643xx_eth_platform_data struct that together describe the PHY
address -- one field (phy_addr) has the address of the PHY, but if
that address is zero, a second field (force_phy_addr) needs to be
set to distinguish the actual address zero from a zero due to not
having filled in the PHY address explicitly (which should mean
'use the default PHY address').
If we are a bit smarter about the encoding of the phy_addr field,
we can avoid the need for a second field -- this patch does that.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Alexander Clouter