Commit Graph

65 Commits

Author SHA1 Message Date
Russell King 3603ab2b62 [ARM] mm 10: allow memory type to be specified with ioremap
__ioremap() took a set of page table flags (specifically the cacheable
and bufferable bits) to control the mapping type.  However, with
the advent of ARMv6, this is far too limited.

Replace the page table flags with a memory type index, so that the
desired attributes can be selected from the mem_type table.

Finally, to prevent silent miscompilation due to the differing
arguments, rename the __ioremap() and __ioremap_pfn() functions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-05 20:59:27 +01:00
Dan Williams d2dd8b1fed [ARM] 4342/2: iop13xx: add resource definitions for the tpmi units
The tpmi units interface with the SAS controller on iop348.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-03 14:03:54 +01:00
Dan Williams fa543f005d [ARM] 4344/1: iop13xx: do not claim both uarts by default on iop342
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-04-30 15:24:56 +01:00
Dan Williams 84c981ffb3 [ARM] 4343/1: iop13xx: automatically detect the internal bus frequency
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-04-30 15:24:54 +01:00
Dan Williams 7dcad376e8 [ARM] 4341/1: iop13xx: fix i/o address translation
PCI devices were being programmed with an incorrect base address value.
This patch moves I/O space into a 16-bit addressable region and corrects
the i/o offset.

Much thanks to Martin Michlmayr for tracking this issue and testing
debug patches.

Cc: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-04-30 15:24:50 +01:00
Russell King 5a84d15906 Merge ARM fixes 2007-02-20 19:13:30 +00:00
Russell King 6a32b935f8 [ARM] Fix iop13xx build error
CC      arch/arm/mach-iop13xx/setup.o
arch/arm/mach-iop13xx/setup.c: In function 'iq8134x_probe_flash_size':
arch/arm/mach-iop13xx/setup.c:210: warning: implicit declaration of function 'ioremap'
arch/arm/mach-iop13xx/setup.c:210: warning: initialization makes pointer from integer without a cast
arch/arm/mach-iop13xx/setup.c:218: warning: implicit declaration of function 'writew'
arch/arm/mach-iop13xx/setup.c:222: warning: implicit declaration of function 'readb'
arch/arm/mach-iop13xx/setup.c:231: warning: implicit declaration of function 'iounmap'
  LD      .tmp_vmlinux1
arch/arm/mach-iop13xx/built-in.o: In function `iop13xx_platform_init':
iq81340mc.c:(.init.text+0x150): undefined reference to `ioremap'
iq81340mc.c:(.init.text+0x21c): undefined reference to `writew'
iq81340mc.c:(.init.text+0x24c): undefined reference to `writew'
iq81340mc.c:(.init.text+0x254): undefined reference to `iounmap'
iq81340mc.c:(.init.text+0x2c4): undefined reference to `readb'
iq81340mc.c:(.init.text+0x2e8): undefined reference to `readb'

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-20 14:56:51 +00:00
Dan Williams 3668b45d46 [ARM] 4187/1: iop: unify time implementation across iop32x, iop33x, and iop13xx
* architecture specific details are handled in asm/arch/time.h
* ARCH_IOP13XX now selects PLAT_IOP
* as suggested by Lennert use ifdef CONFIG_XSCALE to skip the cp_wait on
XSC3

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-17 15:05:40 +00:00
Dan Williams 4434c5c7fd [ARM] 4186/1: iop: remove cp6_enable/disable routines
This functionality is replaced by cp6_trap

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-17 15:04:53 +00:00
Dan Williams 588ef76935 [ARM] 4184/1: iop: cp6 access handler (undef_hook)
Enable svc access to cp6 via an undefined instruction hook.  Do not enable
access for usr code.

This patch also makes iop13xx select PLAT_IOP, this requires a small change
to drivers/i2c/busses/i2c-iop3xx.c.

Per Lennert Buytenhek's note, the cp6 trap routine is moved to arch/arm/plat-iop
Per Nicolas Pitre's note, the cp_wait is skipped since the latency to
return to the faulting function is longer than cp_wait.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-14 15:21:24 +00:00
Dan Williams b0b1d60a64 [ARM] 4077/1: iop13xx: fix __io() macro
Since iop13xx defines the PCI I/O spaces with physical resource addresses
the __io macro needs to perform the physical to virtual conversion.  I
incorrectly assumed that this would be handled by ioremap, but drivers
(like e1000) directly dereference the address returned from __io.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-30 17:05:08 +00:00
Dan Williams 3a2aeda86d [ARM] 4022/1: iop13xx: generic irq fixups
* use irq_chip
* use handle_level_irq

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-19 19:48:53 +00:00
Lennert Buytenhek ab9d90db95 [ARM] 4056/1: iop13xx: fix resource.end off-by-one in flash setup
The struct resource 'end' field is inclusive, the iop13xx flash
setup code got this wrong.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-18 00:14:58 +00:00
Lennert Buytenhek 6d2e857d02 [ARM] 4055/1: iop13xx: fix phys_io/io_pg_offst for iq81340mc/sc
The phys_io/io_pg_offst machine record variables were being set
to bogus values, causing problems when enabling DEBUG_LL.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-18 00:14:56 +00:00
Dan Williams 285f5fa7e9 [ARM] 3995/1: iop13xx: add iop13xx support
The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a
Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory
controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz
PCI-X interface, a x8 PCI-Express interface, and other peripherals to form
a system-on-a-chip RAID subsystem engine.

The iop342 processor replaces the SAS controller with a second Xscale core
for dual core embedded applications.

The iop341 processor is the single core version of iop342.

This patch supports the two Intel customer reference platforms iq81340mc
for external storage and iq81340sc for direct attach (HBA) development.

The developer's manual is available here:
ftp://download.intel.com/design/iio/docs/31503701.pdf

Changelog:
* removed virtual addresses from resource definitions
* cleaned up some unnecessary #include's

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-07 17:20:21 +00:00