then a bunch of driver updates and a handful of new drivers. In terms of
diffstat the Qualcomm and Amlogic drivers are high up there because of all the
clk data introcued by new drivers. The Nvidia Tegra driver had a lot of work
done this cycle too to support suspend/resume and memory controllers. And the
OMAP clk driver got proper clk and reset handling in place.
Rounding out the patches are various updates to remove unused data, mark things
static, correct incorrect data in drivers, etc. All the little things that
improve drivers and maintain code health. I will point out that there's a patch
in here for the GPIO clk driver, that almost nobody uses, which changes
behavior and causes clk_set_rate() to try to change the GPIO gate clk's parent.
Other than that things are fairly well SoC specific here.
Core:
- Add a clk provider API to get current parent index
- Plug a memory leak in clk_unregister() path
New Drivers:
- CGU in Ingenix X1000
- Bitmain BM1880 clks
- Qualcomm MSM8998 GPU clk controllers
- Qualcomm SC7180 GCC and RPMH clk controllers
- Qualcomm QCS404 Q6SSTOP clk controllers
- Add support for the Renesas R-Car M3-W+ (r8a77961) SoC
- Add support for the Renesas RZ/G2N (r8a774b1) SoC
- Add Tegra20/30 External Memory Clock (EMC) support
Updates:
- Make gpio gate clks propagate rate setting up to parent
- Prepare Armada 3700 for suspend to RAM by moving PCIe suspend/resume priority
- Drop unused variables, enums, etc. in various clk drivers
- Convert various drivers to use devm_platform_ioremap_resource()
- Use struct_size() some more in various clk drivers
- Improve Rockchip px30 clk tree
- Add suspend/resume support to Tegra210 clk driver
- Reimplement SOR clks on earlier Tegra SoCs, helping HDMI and DP
- Allwinner DT exports and H6 clk tree fixes
- Proper clk and reset handling for OMAP SoCs
- Revamped TI divider clk to clamp max divider
- Make 1443X/1416X PLL clock structure common for reusing among i.MX8 SoCs
- Drop IMX7ULP_CLK_MIPI_PLL clock, it shouldn't be used
- Add VIDEO2_PLL clock for imx8mq
- Add missing gate clock for pll1/2 fixed dividers on i.MX8 SoCs
- Add sm1 support in the Amlogic audio clock controller
- Switch some clocks on R-Car Gen2/3 to .determine_rate()
- Remove Renesas R-Car Gen2 legacy DT clock support
- Improve arithmetic divisions on Renesas R-Car Gen2 and Gen3
- Improve Renesas R-Car Gen3 SD clock handling
- Add rate table for Samsung exynos542x GPU and VPLL clks
- Fix potential CPU performance degradation after system suspend/resume cycle
on exynos542x SoCs
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl3e6rMRHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSUtWQ//a3epm5t5lQHZjhDJFLYXqavzkGTLcDnF
2+HWNwxLGatvmFqvLAxpB9QlFUntLOdQwjsI47UGKLVNwtXzqafl2yQGrMNYsdR+
6ka0zkytPRuRr+C6cUYUxaoLviDMKi/PXrluOawXbdQ1ZL/5TgURkmEgGglp4Mti
QHp2HO7uSk9pYA8T3TUK+hd9cqLXqW4xMn8MohuWfF3JxoquixOg+N7pE/OeGUyW
NueWWvwKJ86Gtx+OxY8bW3afAzstUynxCUDLC/t7a5y52jxGCwuhHTC/pNcDgYFC
z1H0rnoKG3pE74mm11Mh//zneoqvyzrWYGU6TNcaTxVgODogklGYY6doRLelZ0qc
4HFSqrtkUtx+lI++9Q73LcX5xdogTGxOnNv/hr3rCCR/w9tFmys14JKnfUDQCbhj
qRTFlr9IkIkhfCiRw5+zNo0oRf/hE7IOgYdU2ju31j4w/V5r8TUKPTq2VBh2sJaG
MJKQclaIBJOV5sxgJrI/XoocTes7H3WR0w5rSB1askbhzQnKkrhctPOEB6Rkvtyv
27z5VZb1AmPdYaa6TtHVZ5SQOB3Y9JaEl6t89X61kxk7mgylZlwhASUuBVRZpz53
WIjNfquYGpWnA+vc+SWnlMnaymqtlatGig8k8atdDn+eMiXphktL+gObIF1OFnm1
AhGhUxXf/Aw=
=qJNg
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This merge window we have one small clk provider API in the core
framework and then a bunch of driver updates and a handful of new
drivers. In terms of diffstat the Qualcomm and Amlogic drivers are
high up there because of all the clk data introcued by new drivers.
The Nvidia Tegra driver had a lot of work done this cycle too to
support suspend/resume and memory controllers. And the OMAP clk driver
got proper clk and reset handling in place.
Rounding out the patches are various updates to remove unused data,
mark things static, correct incorrect data in drivers, etc. All the
little things that improve drivers and maintain code health. I will
point out that there's a patch in here for the GPIO clk driver, that
almost nobody uses, which changes behavior and causes clk_set_rate()
to try to change the GPIO gate clk's parent. Other than that things
are fairly well SoC specific here.
Core:
- Add a clk provider API to get current parent index
- Plug a memory leak in clk_unregister() path
New Drivers:
- CGU in Ingenix X1000
- Bitmain BM1880 clks
- Qualcomm MSM8998 GPU clk controllers
- Qualcomm SC7180 GCC and RPMH clk controllers
- Qualcomm QCS404 Q6SSTOP clk controllers
- Add support for the Renesas R-Car M3-W+ (r8a77961) SoC
- Add support for the Renesas RZ/G2N (r8a774b1) SoC
- Add Tegra20/30 External Memory Clock (EMC) support
Updates:
- Make gpio gate clks propagate rate setting up to parent
- Prepare Armada 3700 for suspend to RAM by moving PCIe
suspend/resume priority
- Drop unused variables, enums, etc. in various clk drivers
- Convert various drivers to use devm_platform_ioremap_resource()
- Use struct_size() some more in various clk drivers
- Improve Rockchip px30 clk tree
- Add suspend/resume support to Tegra210 clk driver
- Reimplement SOR clks on earlier Tegra SoCs, helping HDMI and DP
- Allwinner DT exports and H6 clk tree fixes
- Proper clk and reset handling for OMAP SoCs
- Revamped TI divider clk to clamp max divider
- Make 1443X/1416X PLL clock structure common for reusing among i.MX8
SoCs
- Drop IMX7ULP_CLK_MIPI_PLL clock, it shouldn't be used
- Add VIDEO2_PLL clock for imx8mq
- Add missing gate clock for pll1/2 fixed dividers on i.MX8 SoCs
- Add sm1 support in the Amlogic audio clock controller
- Switch some clocks on R-Car Gen2/3 to .determine_rate()
- Remove Renesas R-Car Gen2 legacy DT clock support
- Improve arithmetic divisions on Renesas R-Car Gen2 and Gen3
- Improve Renesas R-Car Gen3 SD clock handling
- Add rate table for Samsung exynos542x GPU and VPLL clks
- Fix potential CPU performance degradation after system
suspend/resume cycle on exynos542x SoCs"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (160 commits)
clk: aspeed: Add RMII RCLK gates for both AST2500 MACs
MAINTAINERS: Add entry for BM1880 SoC clock driver
clk: Add common clock driver for BM1880 SoC
dt-bindings: clock: Add devicetree binding for BM1880 SoC
clk: Add clk_hw_unregister_composite helper function definition
clk: Zero init clk_init_data in helpers
clk: ingenic: Allow drivers to be built with COMPILE_TEST
MAINTAINERS: Update section for Ux500 clock drivers
clk: mark clk_disable_unused() as __init
clk: Fix memory leak in clk_unregister()
clk: Ingenic: Add CGU driver for X1000.
dt-bindings: clock: Add X1000 bindings.
clk: tegra: Use match_string() helper to simplify the code
clk: pxa: fix one of the pxa RTC clocks
clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_by_phandle()
clk: armada-xp: remove unused code
clk: tegra: Fix build error without CONFIG_PM_SLEEP
clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP
clk: tegra: Optimize PLLX restore on Tegra20/30
clk: tegra: Add suspend and resume support on Tegra210
...
There are a few manually-calculated variable-length struct allocations
left, this converts them to use struct_size. Found with the following
git grep command
git grep -A1 'kzalloc.*sizeof[^_].*+'
Signed-off-by: Stephen Kitt <steve@sk2.org>
Link: https://lkml.kernel.org/r/20190927185110.29897-1-steve@sk2.org
Acked-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
[sboyd@kernel.org: Add grep command]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
It is not allowed to sleep to early in the boot process and this may lead
to kernel issues if the bootloader didn't prepare the slow clock and main
clock.
This results in the following error and dump stack on the AriettaG25:
bad: scheduling from the idle thread!
Ensure it is possible to sleep, else simply have a delay.
Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lkml.kernel.org/r/20190920153906.20887-1-alexandre.belloni@bootlin.com
Fixes: 80eded6ce8 ("clk: at91: add slow clks driver")
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
side. The two main highlights in the core framework are the addition of an bulk
clk_get API that handles optional clks and an extra debugfs file that tells the
developer about the current parent of a clk.
The driver updates are dominated by i.MX in the diffstat, but that is mostly
because that SoC has started converting to the clk_hw style of clk
registration. The next big update is in the Amlogic meson clk driver that
gained some support for audio, cpu, and temperature clks while fixing some PLL
issues. Finally, the biggest thing that stands out is the conversion of a large
part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses
less strings and more pointer comparisons to match clk parents and children up.
In general, it looks like we have a lot of little fixes and tweaks here and
there to clk data along with the normal addition of a handful of new drivers
and a couple new core framework features.
Core:
- Add a 'clk_parent' file in clk debugfs
- Add a clk_bulk_get_optional() API (with devm too)
New Drivers:
- Support gated clk controller on MIPS based BCM63XX SoCs
- Support SiLabs Si5341 and Si5340 chips
- Support for CPU clks on Raspberry Pi devices
- Audsys clock driver for MediaTek MT8516 SoCs
Updates:
- Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
- Small frequency support for SiLabs Si544 chips
- Slow clk support for AT91 SAM9X60 SoCs
- Remove dead code in various clk drivers (-Wunused)
- Support for Marvell 98DX1135 SoCs
- Get duty cycle of generic pwm clks
- Improvement in mmc phase calculation and cleanup of some rate defintions
- Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
- Add GPIO, SNVS and GIC clocks for i.MX8 drivers
- Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
- Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
- Add clks for new Exynos5422 Dynamic Memory Controller driver
- Clock definition for Exynos4412 Mali
- Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
- Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
- TI clock probing done from DT by default instead of firmware
- Fix Amlogic Meson mpll fractional part and spread sprectrum issues
- Add Amlogic meson8 audio clocks
- Add Amlogic g12a temperature sensors clocks
- Add Amlogic g12a and g12b cpu clocks
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
- Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
- Add Clock Domain support on Renesas RZ/N1
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl0uBEERHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSWucw/9ELKlfvdxrc8mdIuzt+CpKdNiSG88shXY
hF+vnuE6Jhv5hmlbA/DbplPTAnHT/FQF65/GPQMAYy2wYO6CjleNxQyepiVv4h8/
tWoXu5vYZXubtQyMnYTffREzjYFPBNAscLUhXNwJKRno7nT0qKCk62WgOMfaW/KN
lP5dKmrL7rdJDUvxHEStrwP515Lg5Wkhj3+XzgbgFUKGuGlvHfwUOEZucT++kqhu
Z1vMjPv2ksHQf3r15BsbX/6jMIONEt2Xd6jA3Lm7ebDXJl2hjX4Gq0Kkl5pmkj2w
F0V7Tw4XYk6DkSl7HQaOBgQ8KV0Mw2L8Vj6eEDhUwx6wPGlQ5YTKkUCJkjs0mUyb
UpO3TuPFN2W0hsTNDzwYpjqcfodDn159XJcduv1/ZpIanUvHgx0uVzQ7iwwYwW+l
VR4SipY5AEn9hpief30X7TAUSKsE4do58imYeoGBrq78zdsJaEcDAMX7AcYdXVQ9
ahBS8ME/d1JEBNdRsSW7eTAfu8dZdI08uR8/T37GRG59XyZSjsyVmZ6kHCYrBygF
AyLNMsXMCbW1rOoIpWkuGMD86XZy40laLg8T7WWTaq28t1VQ0BaBTGM4/eEexs3p
FhZ1M7aH+PsDLrI2IGTBt/4xAMv+dhDS7HnxRlOONbWnLWVqmR+tYzF0aCkqJCmd
O2zWCGffeYs=
=mK0C
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This round of clk driver and framework updates is heavy on the driver
update side. The two main highlights in the core framework are the
addition of an bulk clk_get API that handles optional clks and an
extra debugfs file that tells the developer about the current parent
of a clk.
The driver updates are dominated by i.MX in the diffstat, but that is
mostly because that SoC has started converting to the clk_hw style of
clk registration. The next big update is in the Amlogic meson clk
driver that gained some support for audio, cpu, and temperature clks
while fixing some PLL issues. Finally, the biggest thing that stands
out is the conversion of a large part of the Allwinner sunxi-ng driver
to the new clk parent scheme that uses less strings and more pointer
comparisons to match clk parents and children up.
In general, it looks like we have a lot of little fixes and tweaks
here and there to clk data along with the normal addition of a handful
of new drivers and a couple new core framework features.
Core:
- Add a 'clk_parent' file in clk debugfs
- Add a clk_bulk_get_optional() API (with devm too)
New Drivers:
- Support gated clk controller on MIPS based BCM63XX SoCs
- Support SiLabs Si5341 and Si5340 chips
- Support for CPU clks on Raspberry Pi devices
- Audsys clock driver for MediaTek MT8516 SoCs
Updates:
- Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
- Small frequency support for SiLabs Si544 chips
- Slow clk support for AT91 SAM9X60 SoCs
- Remove dead code in various clk drivers (-Wunused)
- Support for Marvell 98DX1135 SoCs
- Get duty cycle of generic pwm clks
- Improvement in mmc phase calculation and cleanup of some rate defintions
- Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
- Add GPIO, SNVS and GIC clocks for i.MX8 drivers
- Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
- Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
- Add clks for new Exynos5422 Dynamic Memory Controller driver
- Clock definition for Exynos4412 Mali
- Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
- Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
- TI clock probing done from DT by default instead of firmware
- Fix Amlogic Meson mpll fractional part and spread sprectrum issues
- Add Amlogic meson8 audio clocks
- Add Amlogic g12a temperature sensors clocks
- Add Amlogic g12a and g12b cpu clocks
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
- Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
- Add Clock Domain support on Renesas RZ/N1"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits)
clk: consoldiate the __clk_get_hw() declarations
clk: sprd: Add check for return value of sprd_clk_regmap_init()
clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
clk: Add Si5341/Si5340 driver
dt-bindings: clock: Add silabs,si5341
clk: clk-si544: Implement small frequency change support
clk: add BCM63XX gated clock controller driver
devicetree: document the BCM63XX gated clock bindings
clk: at91: sckc: use dedicated functions to unregister clock
clk: at91: sckc: improve error path for sama5d4 sck registration
clk: at91: sckc: remove unnecessary line
clk: at91: sckc: improve error path for sam9x5 sck register
clk: at91: sckc: add support to free slow clock osclillator
clk: at91: sckc: add support to free slow rc oscillator
clk: at91: sckc: add support to free slow oscillator
clk: rockchip: export HDMIPHY clock on rk3228
clk: rockchip: add watchdog pclk on rk3328
clk: rockchip: add clock id for hdmi_phy special clock on rk3228
clk: rockchip: add clock id for watchdog pclk on rk3328
clk: at91: sckc: add support for SAM9X60
...
Use at91 specific functions to free all resources in case of error.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Different IPs uses different bit offsets in registers for the same
functionality, thus adapt the driver to support this.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The slow clock of SAMA5D4 has no bypass support thus remove it.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 3029 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The sama5d3 slow RC oscillator as a different startup time than all the
previous SoCs. Handle that using its own compatible.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Remove the need for child nodes in the sckc binding and register the whole
sckc tree (3 clocks in total) from the sckc node.
DT backward compatibility is kept by looking for properties in child nodes
when they are not present in the sckc node.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Assume that if the oscillator is enabled (OSC32EN bit is present), the
delay has already elapsed as the bootloader probably waited for the
oscillator to settle. This could waste up to 1.2s.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Starting with sama5d4, the crystal oscillator is always enabled at startup
and the SCKC doesn't have an OSC32EN bit anymore.
Add support for that new controller.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Move all clocks related to the slow clock controller to sckc.c. This avoids
extern definitions and allows to remove sckc.h
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
[sboyd@codeaurora.org: Mark some functions static]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
AT91 slow clk is a clk multiplexer.
In some SoCs (sam9x5, sama5, sam9g45 families) this multiplexer can
choose among 2 sources: an internal RC oscillator circuit and an oscillator
using an external crystal.
In other Socs (sam9260 family) the multiplexer source is hardcoded with
the OSCSEL signal.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Claudiu Beznea