factorise some generic infrastructure to assist looking up struct clks
for the ARM & SH architecture.
as the code is identical at 99%
put the arch specific code for allocation as example in asm/clkdev.h
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Setting sysclk rate will be useful in cases where the
sysclk is not at a fixed ratio to the PLL output but
can asynchronously be changed.
This support forms the basis of attempt to keep the AEMIF
clock constant on OMAP-L138 even as PLL0 output changes
as ARM clock is changed to save power.
This patch has been tested on OMAP-L138.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The earlier watchdog reset mechanism had a couple of limitations. First, it
embedded a reference to "davinci_wdt_device" inside common code. This
forced all derived platforms (da8xx and tnetv107x) to define such a device.
This also would have caused problems in including multiple socs in a single
build due to symbol redefinition.
With this patch, davinci_watchdog_reset() now takes the platform device as an
argument. The davinci_soc_info struct has been extended to include a reset
function and a watchdog platform_device. arch_reset() then uses these
elements to reset the system in a SoC specific fashion.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch allows socs to override the divider ratio mask by setting an
optional field (div_ratio_mask) in the pll_data structure.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The current clock control code always gates the clock (PSC state Disable = 2)
on clk_disable(). Some on-chip peripherals (e.g. LCD controller on TNETV107X)
need to be put into SwRstDisable = 0 on clock disable, to maintain
hardware sanity.
This patch extends the davinci_psc_config() arguments to pass in the desired
module state instead of a boolean enable/disable. Further, clk_disable() now
checks for the PSC_SWRSTDISABLE clk flag before selecting the target state.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Remove unneeded 'struct davinci_clk' wrapper around 'struct clk_lookup'
and use clkdev_add_table() to add the list of clocks in one go.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
psc.h contains register defines for PSC module which
need to be accessed in assembly code which helps the
DA850/OMAP-L138 SoC go to sleep. Shutting down DDR clock
using PSC is a part of the sleep procedure.
Also, the PLL related hardware definitions in clock.h are
needed in assembly code to bypass the DDR2 PLL.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
As suspend support is added, the code supporting
the suspend operation needs to bypass PLLs and
needs to access the same wait time values as the
PLL code in clock.c.
To facilitate this, move the PLL wait times to
clock.h where they can be accessed by suspend code.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Replace badly chosen 'psc_ctlr' name of the 'struct clk' field (PSC already
means "Power and Sleep Controller", so the '_ctlr' postfix makes the name
tautological) with technically correct 'gpsc' (Global PSC -- which contains
all the module registers).
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The patch allows Async3 clock source to be selected between PLL1 SYSCLK2
and PLL0 SYSCLK2.
Having Async3 source from PLL1 SYSCLK2 allows peripherals on that
domain to remain unaffected by frequency scaling on PLL0.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
clk_round_rate, clk_set_rate have been updated to handle dynamic
frequency changes.
The motivation behind the changes is to support dynamic CPU frequency
change.
davinci_set_pllrate() changes the PLL rate of a given PLL. This function
has been presented as a generic function though it has been tested only
on OMAP-L138 EVM. No other currently available DaVinci device will probably
use this function, but any future device specific changes will hopefully be
small enough to get taken care using a cpu_is_xxx() macro.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Make clock rate recalculation easy by having a re-calculate
function for each clock.
The existing functions for calculation of output rates of PLL
and PLL-derived sysclks have been convered to the new
re-calculate API.
A new function is introduced to take care of rate
(re)calculation for leaf clocks.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Achieve easy top down traversal of clock tree by keeping
track of each clock's list of children.
This is useful in supporting DVFS where clock rates of
all children need to be updated in an efficient manner.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The current code to support the DaVinci Power and Sleep Controller (PSC)
assumes that there is only one controller. This assumption is no longer
valid so expand the support to allow greater than one PSC.
To accomplish this, put the base addresses for the PSCs in the SoC
infrastructure so it can be referenced by the PSC code. This also
requires adding an extra parameter to davinci_psc_config() to specify
the PSC that is to be enabled/disabled.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This is a significant rework of the low-level clock, PLL and Power
Sleep Controller (PSC) implementation for the DaVinci family. The
primary goal is to have better modeling if the hardware clocks and
features with the aim of DVFS functionality.
Highlights:
- model PLLs and all PLL-derived clocks
- model parent/child relationships of PLLs and clocks
- convert to new clkdev layer
- view clock frequency and refcount via /proc/davinci_clocks
Special thanks to significant contributions and testing by David
Brownell.
Cc: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Support clock control driver for TI DaVinci SoC
Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com>
Signed-off-by: Kevin Hilman <khilman@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Jean-Christop PLAGNIOL-VILLARD