Commit Graph

3 Commits

Author SHA1 Message Date
Scott Wood 4267ea72bb oprofile/fsl emb: Don't set MSR[PMM] until after clearing the interrupt.
On an arch 2.06 hypervisor, a pending perfmon interrupt will be delivered
to the hypervisor at any point the guest is running, regardless of
MSR[EE].  In order to reflect this interrupt, the hypervisor has to mask
the interrupt in PMGC0 -- and set MSRP[PMMP] to intercept futher guest
accesses to the PMRs to detect when to unmask (and prevent the guest from
unmasking early, or seeing inconsistent state).

This has the side effect of ignoring any changes the guest makes to
MSR[PMM], so wait until after the interrupt is clear, and thus the
hypervisor should have cleared MSRP[PMMP], before setting MSR[PMM].  The
counters wil not actually run until PMGC0[FAC] is cleared in
pmc_start_ctrs(), so this will not reduce the effectiveness of PMM.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-14 00:53:05 -05:00
Michael Ellerman e2ff7544e1 powerpc/oprofile: Remove unused dump_pmcs() in FSL oprofile
It's still in the git history if anyone wants it.

Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-05-19 00:46:13 -05:00
Andy Fleming 39aef685af [POWERPC] Made FSL Book-E PMC support more generic
Some of the more recent e300 cores have the same performance monitor
implementation as the e500.  e300 isn't book-e, so the name isn't
really appropriate.  In preparation for e300 support, rename a bunch
of fsl_booke things to say fsl_emb (Freescale Embedded Performance Monitors).

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-02-05 23:34:14 -06:00