Commit Graph

1417 Commits

Author SHA1 Message Date
Mathias Nyman 41939e699c pinctrl: baytrail: resolve unbalanced IRQ wake disable warning
Add the IRQCHIP_SKIP_SET_WAKE flag to baytrail gpio irq_chip
to resolve unbalaced IRQ wake disable warnings.

Suggested-by: Borun Fu <borun.fu@intel.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-09-10 14:25:51 +02:00
Tomasz Figa f6a8249f9e pinctrl: exynos: Lock GPIOs as interrupts when used as EINTs
Currently after configuring a GPIO pin as an interrupt related pinmux
registers are changed, but there is no protection from calling
gpio_direction_*() in a badly written driver, which would cause the same
pinmux register to be reconfigured for regular input/output and this
disabling interrupt capability of the pin.

This patch addresses this issue by moving pinmux reconfiguration to
.irq_{request,release}_resources() callback of irq_chip and calling
gpio_lock_as_irq() helper to prevent reconfiguration of pin direction.

Setting up a GPIO interrupt on Samsung SoCs is a two-step operation -
in addition to trigger configuration in a dedicated register, the pinmux
must be also reconfigured to GPIO interrupt, which is a different function
than normal GPIO input, although I/O-wise they both behave in the same way
and gpio_get_value() can be used on a pin configured as IRQ as well.

Such design implies subtleties such as gpio_direction_input() not having
to fail if a pin is already configured as an interrupt nor change the
configuration to normal input. But the FLAG_USED_AS_IRQ set in gpiolib by
gpio_lock_as_irq() is only used to check that gpio_direction_output() is
not called, it's not used to prevent gpio_direction_input() to be called.
So this is not a complete solution for Samsung SoCs but it's definitely a
move in the right direction.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
[javier: use request resources instead of startup and expand commit message]
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-08-21 07:24:29 -05:00
Hans Wennborg 4b6fe45a79 pinctrl: pinctrl-at91.c: fix decimal printf format specifiers prefixed with 0x
The prefix suggests the number should be printed in hex, so use
the %x specifier to do that.

Found by using regex suggested by Joe Perches.

Signed-off-by: Hans Wennborg <hans@hanshq.net>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-08-17 09:15:44 -05:00
Patrice CHOTARD 1d54f0fd58 pinctrl: abx500: remove useless check
pctldev can't be NULL at this stage so remove the check

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-08-17 09:15:44 -05:00
Dan Carpenter 8a3cfb7c17 pinctrl: tegra-xusb: testing wrong variable in probe()
There is a cut and paste bug so we test the wrong variable.  "err" is
never less than zero at this point.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-08-17 09:15:44 -05:00
Dan Carpenter 8e1594db7e pinctrl: tegra-xusb: fix an off by one test
This shoudld be ">= ARRAY_SIZE()" instead of "> ARRAY_SIZE()".

Fixes: dc0a393866 ('pinctrl: Add NVIDIA Tegra XUSB pad controller support')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-08-17 09:15:44 -05:00
Sonny Rao 99e872d953 pinctrl: rockchip: fix rk3288 gpio0 configuration
On rk3288, for gpio bank 0, the registers which configure pull-up,
iomux, and drive strength don't implement the enable bits in the upper
half of the register, unlike the other gpio configuration registers,
and so the kernel must perform a read-modify-write of the register to
update a particular gpio in that bank.

The current code is actually clobbering the contents of the register,
so this fixes it by using regmap_update_bits and masking out only the
bits which require updating.  In the case of bank0 on rk3288 the upper
enable bits will just get ignored, and the other configurations won't
get clobbered.

Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-08-17 09:15:43 -05:00
Sergei Shtylyov 302fb17817 sh-pfc: r8a7791: fix CAN pin groups
I had made last-minute changes before submitting the patch "sh-pfc: r8a7791:
add CAN pin groups"; now I'm seeing that they weren't complete: I had missed
update to the pin group names in pin[01]_groups[]. Drop the "_a" suffixes there.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-08-17 09:15:43 -05:00
Linus Torvalds 10c8e05620 ARM: SoC driver changes for 3.17
A handful of driver-related changes. We've had a bunch of them going in through
 other branches as well, so it's only a part of what we really have this release.
 
 Larger pieces are:
 
 * Removal of a now unused PWM driver for atmel
   - This includes AVR32 changes that have been appropriately acked.
 * Performance counter support for the arm CCN interconnect
 * OMAP mailbox driver cleanups and consolidation
 * PCI and SATA PHY drivers for SPEAr 13xx platforms
 * Redefinition (with backwards compatibility!) of PCI DT bindings for Tegra to
   better model regulators/power.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJT5DrJAAoJEIwa5zzehBx3wkkP/iwEfEK5mMon9KEe4DcKTKNq
 Z6xyWuMQNHKdfBFpABs6AsHQCKDc7KK6gN3+2zLLHEJ4XGDPZ2g2NaX3oRPJlaay
 BDK7rQfIZyi4tmbOnlEv1BDTYgirYBPMwk9RyNo/04Ug3W+Y67aSVo44zkNFBWaJ
 GbcX/zYsrsfvdawuQMW6V/A835s3Kq5Zhv1ikPr8gDDjswZRBAT6i7FYpBSHQ8K8
 bH6C1891Xit6rxXSLXJyrtM8CAet7PtLTqNr/IKdUaJnGD+fJm5EonxW+g8gvhN8
 gOEkm3nM60++kdDlzZCQVNr0m1+ih6NNCr6bDLO6rIRpAJM2O+YrN1rWuZaJOu1A
 pIvifk+wWHT+o52pXk8g9fK4n/ZJydK3IBzDePHMrIROOEiW5tLE3WA+u3NSfMfH
 WegMt9E2dcB+5gXPeejZ9gFbAHnh2S1oVTZfCYXtuOHrYiEU9U0FA3eRYvJEE2po
 k8sdiOn7Vc65O1QZ+xZNbLABpAHaye7X2evOJyhSutzHE/AtUvT4vuCAZ0tggXyD
 E1qVKngVW/NvcoFbwYeidq4bOVgiAEn3idZgF5gEq1mq7LzetXUQAcZAOQfLWHLQ
 RrXufS7Ez8pSCG74y0AFReVfQH2PgWHPqGUGj99NXgQauexc/vR1Hc5Iqb8liGNJ
 n6i8RqvvQ4KYcmHEXDIT
 =fsP6
 -----END PGP SIGNATURE-----

Merge tag 'drivers-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver changes from Olof Johansson:
 "A handful of driver-related changes.  We've had a bunch of them going
  in through other branches as well, so it's only a part of what we
  really have this release.

  Larger pieces are:

   - Removal of a now unused PWM driver for atmel
     [ This includes AVR32 changes that have been appropriately acked ]
   - Performance counter support for the arm CCN interconnect
   - OMAP mailbox driver cleanups and consolidation
   - PCI and SATA PHY drivers for SPEAr 13xx platforms
   - Redefinition (with backwards compatibility!) of PCI DT bindings for
     Tegra to better model regulators/power"

Note: this merge also fixes up the semantic conflict with the new
calling convention for devm_phy_create(), see commit f0ed817638 ("phy:
core: Let node ptr of PHY point to PHY and not of PHY provider") that
came in through Greg's USB tree.

Semantic merge patch by Stephen Rothwell <sfr@canb.auug.org.au> through
the next tree.

* tag 'drivers-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (38 commits)
  bus: arm-ccn: Fix error handling at event allocation
  mailbox/omap: add a parent structure for every IP instance
  mailbox/omap: remove the private mailbox structure
  mailbox/omap: consolidate OMAP mailbox driver
  mailbox/omap: simplify the fifo assignment by using macros
  mailbox/omap: remove omap_mbox_type_t from mailbox ops
  mailbox/omap: remove OMAP1 mailbox driver
  mailbox/omap: use devm_* interfaces
  bus: ARM CCN: add PERF_EVENTS dependency
  bus: ARM CCN PMU driver
  PCI: spear: Remove spear13xx_pcie_remove()
  PCI: spear: Fix Section mismatch compilation warning for probe()
  ARM: tegra: Remove legacy PCIe power supply properties
  PCI: tegra: Remove deprecated power supply properties
  PCI: tegra: Implement accurate power supply scheme
  ARM: SPEAr13xx: Update defconfigs
  ARM: SPEAr13xx: Add pcie and miphy DT nodes
  ARM: SPEAr13xx: Add bindings and dt node for misc block
  ARM: SPEAr13xx: Fix static mapping table
  phy: Add drivers for PCIe and SATA phy on SPEAr13xx
  ...
2014-08-08 11:34:32 -07:00
Linus Torvalds d4e1f5a14e ARM: SoC device-tree changes for 3.17
Unlike the board branch, this keeps having large sets of changes for
 every release, but that's quite expected and is so far working well.
 
 Most of this is plumbing for various device bindings and new platforms,
 but there's also a bit of cleanup and code removal for things that
 are moved from platform code to DT contents (some OMAP clock code in
 particular).
 
 There's also a pinctrl driver for tegra here (appropriately acked),
 that's introduced this way to make it more bisectable.
 
 I'm happy to say that there were no conflicts at all with this branch
 this release, which means that changes are flowing through our tree as
 expected instead of merged through driver maintainers (or at least not
 done with conflicts).
 
 There are several new boards added, and a couple of SoCs. In no particular
 order:
 
 * Rockchip RK3288 SoC support, including DTS for a dev board that they
   have seeded with some community developers.
 * Better support for Hardkernel Exynos4-based ODROID boards.
 * CCF conversions (and dtsi contents) for several Renesas platforms.
 * Gumstix Pepper (TI AM335x) board support
 * TI eval board support for AM437x
 * Allwinner A23 SoC, very similar to existing ones which mostly has
   resulted in DT changes for support. Also includes support for an Ippo
   tablet with the chipset.
 * Allwinner A31 Hummingbird board support, not to be confused with the
   SolidRun i.MX-based Hummingboard.
 * Tegra30 Apalis board support
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJT5DqvAAoJEIwa5zzehBx3tm0QAJk8zFyZuMhUPz6SoZTtO9ti
 zojZ2218oqLRDfLSYdJx/3QE7gb2ef0e2S6FrthecdAY8sqZzDddL7M/cCf1WSgy
 +D4dD1UEq+W/hOeEwIWyo3GR/71exgo/LMTIw8HOJh5c9fanQ2wNChNetCgh8b4u
 sVOEMmP1UTO2W7mH9cCRhWXFifBNi0yNl1QBYnLPzM2CbSEa4qQRarTn/94NSEiY
 U9XgzysklvYEW/30wcEkz8ZonKbJrtP+zEjODU4wN/muhHECeTehDrkJq0WEK/3C
 3ptko2xQGURNaLM6HVvQS9qkXxyhCeZxqkELpjkjjM+YPFN8wdHu7gDctGZlDr39
 LQ2pZF6K8vaFvxp3UM2wzdDeoNi3rxguzpFoBmfRP5NWguDrOvjT3w8W4hO9q04J
 8SqMGca0av9myHmeSjtRRg5rmcC3kBbOgSN6siVJ8W80rHT7tnFjl6eCawDreQzn
 szFzGaOOUnf/kJ/00vzm1dCuluowFPdSYgW3aamZhfkqu2qYJ8Ztuooz5eZGKtex
 zlUfKtpL26gnamoUT42K7E8J968AjHjUc/zimwYzIgHCzTTApYGJQcbD/Y28b8QH
 gTvhRxP+0kFb+NNq4IHStVMvJrFOPvzOHXcL8x07HqTxrl7W4XoW+KJxCJOk433W
 5NJ9s4tEmiTRMtFL1kv6
 =xxlY
 -----END PGP SIGNATURE-----

Merge tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device-tree changes from Olof Johansson:
 "Unlike the board branch, this keeps having large sets of changes for
  every release, but that's quite expected and is so far working well.

  Most of this is plumbing for various device bindings and new
  platforms, but there's also a bit of cleanup and code removal for
  things that are moved from platform code to DT contents (some OMAP
  clock code in particular).

  There's also a pinctrl driver for tegra here (appropriately acked),
  that's introduced this way to make it more bisectable.

  I'm happy to say that there were no conflicts at all with this branch
  this release, which means that changes are flowing through our tree as
  expected instead of merged through driver maintainers (or at least not
  done with conflicts).

  There are several new boards added, and a couple of SoCs.  In no
  particular order:

   - Rockchip RK3288 SoC support, including DTS for a dev board that
     they have seeded with some community developers.
   - Better support for Hardkernel Exynos4-based ODROID boards.
   - CCF conversions (and dtsi contents) for several Renesas platforms.
   - Gumstix Pepper (TI AM335x) board support
   - TI eval board support for AM437x
   - Allwinner A23 SoC, very similar to existing ones which mostly has
     resulted in DT changes for support.  Also includes support for an
     Ippo tablet with the chipset.
   - Allwinner A31 Hummingbird board support, not to be confused with
     the SolidRun i.MX-based Hummingboard.
   - Tegra30 Apalis board support"

* tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (334 commits)
  ARM: dts: Enable USB host0 (EHCI) on rk3288-evb
  ARM: dts: add rk3288 ehci usb devices
  ARM: dts: Turn on USB host vbus on rk3288-evb
  ARM: tegra: apalis t30: fix device tree compatible node
  ARM: tegra: paz00: Fix some indentation inconsistencies
  ARM: zynq: DT: Clarify Xilinx Zynq platform
  ARM: dts: rockchip: add watchdog node
  ARM: dts: rockchip: remove pinctrl setting from radxarock uart2
  ARM: dts: Add missing pinctrl for uart0/1 for exynos3250
  ARM: dts: Remove duplicate 'interrput-parent' property for exynos3250
  ARM: dts: Add TMU dt node to monitor the temperature for exynos3250
  ARM: dts: Specify MAX77686 pmic interrupt for exynos5250-smdk5250
  ARM: dts: cypress,cyapa trackpad is exynos5250-Snow only
  ARM: dts: max77686 is exynos5250-snow only
  ARM: zynq: DT: Remove DMA from board DTs
  ARM: zynq: DT: Add CAN node
  ARM: EXYNOS: Add exynos5260 PMU compatible string to DT match table
  ARM: dts: Add PMU DT node for exynos5260 SoC
  ARM: EXYNOS: Add support for Exynos5410 PMU
  ARM: dts: Add PMU to exynos5410
  ...
2014-08-08 11:16:58 -07:00
Linus Torvalds e0b8b78651 This is the bulk pin control changes for the v3.17 merge
development cycle:
 
 - Get rid of the .disable() callback from the driver callback
   vtable. This callback was abused and counterintuitive since
   a pin or group of pins can be said to always be in some
   setting, and never really disabled. We now only enable a
   certain muxing, and move between some certain muxings, we
   never "disable" a mux setting.
 
 - Some janitorial moving the MSM, Samsung and Nomadik and
   drivers to their own subdirectories for a clearer view in
   the subsystem. This will continue.
 
 - Kill off the use of the return value from gpiochip_remove(),
   this will be done in parallel in the GPIO subsystem and
   hopefully not trigger too many unchecked return value
   warnings before we get rid of this altogether.
 
 - A huge set of changes and improvements to the Allwinner
   sunxi drivers especially for their latest A23 and A31 SoCs,
   and some ground work for the new sun8i platform family.
 
 - A large set of Rockchip driver improvements adding support
   for the RK3288 SoC.
 
 - Advances in migration of older Freescale platforms to pin
   control, especially i.MX1.
 
 - Samsung and Exynos improvements.
 
 - Support for the Qualcomm MSM8960 SoC.
 
 - Use the gpiolib irqchip helpers for the ST SPEAr and
   Intel Baytrail drivers.
 
 - A bunch of nice janitorial work done with cppcheck.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJT41HwAAoJEEEQszewGV1zVN0QAMJOJcsjYyHG+b/y0upJ5n1c
 tyPelyxKrpGUUTvTsO5LiqvoIfa2E/DrwXupRAC4zAXvb+x3TUGkiluK4Yxl5e56
 AqjePnSydqqHiRZOK4Q06W7VwGUoxLltDmDPTcra+DAaijIeKUPMQE1MvcPxisMe
 IR7PZN58JYCG3ZV5yjwfBBxcRAm8KiiwHvQdBywPIGGvvmpy1X+U96U869nQgUH2
 70lpJVPx75bhyAFk99bE9nAnroZeRR7mvijjf26ssyAFNqeJ0K7Xlom+NtpHdiw0
 lsDKdBiAWVbZON/7Pc24gpHzhBoIYdA/6LxPA8Xz4QVFRmfxmNkZhuXZnZ7Dbuj2
 xv9HtnjExqjZcfeNyUlO0iQDEQIUN/oPkaBS2G8DNZ/bmQqC8EzkIFh6F72KO1s2
 7FU214LcuBYuAa3HvNLmgtjSkgou8tTMj58rnZ1XDr2mI9tzlrwI3i6ZrJZWKDur
 NIoRAcUZkFiMpXxqLbk4UXzDvuJgrzaFiQ2PkxTXAlC2DjXz+gXPzPIOSD5LTaHE
 k3WvZfuGK2iPoKeDHaLx2qEl9PoD5hz1JH3o+bgOKkRZG2gEJWd02JwhuPyRPLfc
 TeBgmdYS2t2MBS21VsqoObw8336oCHJu7tDAxTkAalLsZy9MV2WqThhZoYggZ/Rq
 yMqCr8vfd2pRVtwYe7Wc
 =t1pR
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v3.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pinctrl updates from Linus Walleij:
 "This is the bulk pin control changes for the v3.17 merge development
  cycle:

   - get rid of the .disable() callback from the driver callback vtable.

     This callback was abused and counterintuitive since a pin or group
     of pins can be said to always be in some setting, and never really
     disabled.  We now only enable a certain muxing, and move between
     some certain muxings, we never "disable" a mux setting

   - some janitorial moving the MSM, Samsung and Nomadik and drivers to
     their own subdirectories for a clearer view in the subsystem.  This
     will continue

   - kill off the use of the return value from gpiochip_remove(), this
     will be done in parallel in the GPIO subsystem and hopefully not
     trigger too many unchecked return value warnings before we get rid
     of this altogether

   - a huge set of changes and improvements to the Allwinner sunxi
     drivers especially for their latest A23 and A31 SoCs, and some
     ground work for the new sun8i platform family

   - a large set of Rockchip driver improvements adding support for the
     RK3288 SoC

   - advances in migration of older Freescale platforms to pin control,
     especially i.MX1

   - Samsung and Exynos improvements

   - support for the Qualcomm MSM8960 SoC

   - use the gpiolib irqchip helpers for the ST SPEAr and Intel Baytrail
     drivers

   - a bunch of nice janitorial work done with cppcheck"

* tag 'pinctrl-v3.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (61 commits)
  pinctrl: baytrail: Convert to use gpiolib irqchip
  pinctrl: sunxi: number gpio ranges starting from 0
  pinctrl: sunxi: use gpiolib API to mark a GPIO used as an IRQ
  pinctrl: rockchip: add drive-strength control for rk3288
  pinctrl: rockchip: add separate type for rk3288
  pinctrl: rockchip: set is_generic in pinconf_ops
  pinctrl: msm: drop negativity check on unsigned value
  pinctrl: remove all usage of gpio_remove ret val in driver/pinctl
  pinctrl: qcom: Make muxing of gpio function explicit
  pinctrl: nomadik: move all Nomadik drivers to subdir
  pinctrl: samsung: Group all drivers in a sub-dir
  sh-pfc: sh73a0: Introduce the use of devm_regulator_register
  sh-pfc: Add renesas,pfc-r8a7791 to binding documentation
  pinctrl: msm: move all qualcomm drivers to subdir
  pinctrl: msm: Add msm8960 definitions
  pinctrl: samsung: Allow pin value to be initialized using pinfunc
  pinctrl: samsung: Allow grouping multiple pinmux/pinconf nodes
  pinctrl: exynos: Consolidate irq_chips of GPIO and WKUP EINTs
  pinctrl: samsung: Handle GPIO request and free using pinctrl helpers
  pinctrl: samsung: Decouple direction setting from pinctrl
  ...
2014-08-07 17:20:53 -07:00
Mika Westerberg e1ee5c578f pinctrl: baytrail: Convert to use gpiolib irqchip
Instead of open-coding irqchip handling in the driver we can take advantage
of the new irqchip helpers provided by the gpiolib core.

While doing this we also make sure that we call gpiochip_irqchip_add()
after the gpiochip itself is registered as required.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-28 12:21:00 +02:00
Chen-Yu Tsai 343f132752 pinctrl: sunxi: number gpio ranges starting from 0
The pinctrl-sunxi driver originally used the pin number as the gpio
range offset. This resulted in large, bogus gpio numbers for the
new sun6i-a31-r pinctrl devices.

This patch makes the driver number the gpios ranges starting from an
offset of 0, by subtracting the pin_base number from the pin number.
This also makes the system-wide gpio number match the pin number.

Tested on sun8i with sysfs exported gpios.

This patch also changes the GPIO bindings for R_PIO:

    gpios = <&r_pio B N flag>;

Where B originally was the pinbank label (L or M) counted from A,
with this patch it becomes (L or M) counted from its pinbank base (L).

Thus

    gpios = <&r_pio 10 11 0>; /* PL11 */

becomes

    gpios = <&r_pio 0 11 0>; /* PL11 */

IMO this is correct, as the binding shows the bank offset and pin offset
within the bank for the GPIO controller. But I'm worried it might be a
bit confusing.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-28 12:14:33 +02:00
Chen-Yu Tsai f83549d61d pinctrl: sunxi: use gpiolib API to mark a GPIO used as an IRQ
When an IRQ is started on a GPIO line, mark this GPIO as IRQ in
the gpiolib so we can keep track of the usage centrally.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-28 12:10:46 +02:00
Heiko Stübner b547c8007e pinctrl: rockchip: add drive-strength control for rk3288
The rk3288 is the first Rockchip soc handling the drive strength on a per-pin
basis, while the older ones can set the drive-strength only for specific
pin-groups. Therefore limit setting the drive-strength to this soc for now.

Signed-off-by: Heiko Stübner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-23 16:41:16 +02:00
Heiko Stübner 66d750e1d0 pinctrl: rockchip: add separate type for rk3288
An upcoming pinctrl function of the rk3288 differs again from everything else,
so we'll need a separate type for it.

Signed-off-by: Heiko Stübner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-23 16:39:41 +02:00
Heiko Stübner ed62f2f255 pinctrl: rockchip: set is_generic in pinconf_ops
The rockchip pinctrl driver implements the generic pinconfig, therefore
also state this, so that the default pinconf dump functions work.

Signed-off-by: Heiko Stübner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-23 16:37:40 +02:00
Andrey Utkin 1c34955102 pinctrl: msm: drop negativity check on unsigned value
[linux-3.16-rc5/drivers/pinctrl/pinctrl-msm.c:145]: (style) Checking if
unsigned variable 'mux_bit' is less than zero.

    if (WARN_ON(g->mux_bit < 0))
        return -EINVAL;

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=80491
Reported-by: David Binderman <dcb314@hotmail.com>
Signed-off-by: Andrey Utkin <andrey.krieger.utkin@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-23 15:24:40 +02:00
abdoulaye berthe b4e7c55dab pinctrl: remove all usage of gpio_remove ret val in driver/pinctl
Signed-off-by: abdoulaye berthe <berthe.ab@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-22 16:34:12 +02:00
Bjorn Andersson 144ef62645 pinctrl: qcom: Make muxing of gpio function explicit
Instead of relying on pinmux->disable(), make the gpio function an
explicit function for all pins that supports it.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-22 16:31:58 +02:00
Olof Johansson 58cd070a84 ARM: tegra: Add XUSB pad controller support
Adds device tree bindings and a driver for the XUSB pad controller found
 on Tegra114 and later. This is a prerequisites for PCIe, SATA and XUSB
 drivers which are all currently being reviewed or pending for merge.
 
 This is a separate branch in case it needs to be pulled into the pinctrl
 tree to resolve conflicts.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABAgAGBQJTySWRAAoJEN0jrNd/PrOhIXsP/2Zfx2ctY5i9PTsu8V8tnuQ7
 IO6mNKZGE9nocoi64Nq/+tBiQn+X1y0Pu5uHJt9a4FCOpNY5TsgwN3d3PCoRNbqu
 1Buqjla/cgAZ+E2WkqSqvZLxlTIAIlFGxNNucBgXkn1euebsNkYWgdcxucUBqdUE
 F1AgsZFK6wuZIONZIRTBWUxZwSiu5Nh0Fd6Qg6yZbMTs8mKZVesm0KHglZiAH/m9
 h6htGQpfwxGqnk1O3Cm0I6dwuhMLzoVCPdnPfDx5K5mTNeOmfPcRsJ6au9S1eqM8
 ZI0o+aCWiOi42UBLcCX7voriPSsTq0Ur5igmo+Gn3Rfa00aACuy3FPu8a3+453ID
 nnG3zo2vLDO5MkRbCqgvW7L29Q6wtO7Xx5o608tetvCC4MXItj5OSzowp57m9OIw
 PP1pYc3fgJeAbh8tHAc81tHUbV0mNYVLxN44erg3SVO168+clHVDWdTYqMFUtGs8
 kPKsgJHeQKW5tKlOf919+oCaIje64vhzwOTN+L0M+TPUD8S8qkBfFEcNQkFPZ5GA
 v7xyAgTHlTcwpkKRt4fdI97PfPpu47+wVu3d0Ivv/zzE5oPuQqdXMgeWzBrMUysh
 nUycFAxiq9JljaBMNAaLJH+S+eX8yrI8GoOe+s+dQrVk2vFmKKvSDU5wbT4jQvxh
 T3tUy/gem9p19dVcQhpU
 =oUBt
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-3.17-xusb-padctl' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt

Merge "ARM: tegra: Add XUSB pad controller support" from Thierry Reding:

Adds device tree bindings and a driver for the XUSB pad controller found
on Tegra114 and later. This is a prerequisites for PCIe, SATA and XUSB
drivers which are all currently being reviewed or pending for merge.

This is a separate branch in case it needs to be pulled into the pinctrl
tree to resolve conflicts.

* tag 'tegra-for-3.17-xusb-padctl' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  pinctrl: Add NVIDIA Tegra XUSB pad controller support
  of: Add NVIDIA Tegra XUSB pad controller binding

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-19 12:49:24 -07:00
Maxime COQUELIN 7a2deccf0e pinctrl: st: Fix irqmux handler
st_gpio_irqmux_handler() reads the status register to find out
which banks inside the controller have pending IRQs.
For each banks having pending IRQs, it calls the corresponding handler.

Problem is that current code restricts the number of possible banks inside the
controller to ST_GPIO_PINS_PER_BANK. This define represents the number of pins
inside a bank, so it shouldn't be used here.

On STiH407, PIO_FRONT0 controller has 10 banks, so IRQs pending in the two
last banks (PIO18 & PIO19) aren't handled.

This patch replace ST_GPIO_PINS_PER_BANK by the number of banks inside the
controller.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: <stable@vger.kernel.org> #v3.15+
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-15 20:55:15 +02:00
Linus Walleij 3a19805920 pinctrl: nomadik: move all Nomadik drivers to subdir
We have a bunch of Nomadik family pin control drivers, so let's
move them into their own subdirectory.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 15:01:35 +02:00
Thierry Reding dc0a393866 pinctrl: Add NVIDIA Tegra XUSB pad controller support
The XUSB pad controller found on NVIDIA Tegra SoCs provides several pads
that lanes can be assigned to in order to support a variety of interface
options: USB 2.0, USB 3.0, PCIe and SATA.

In addition to the pin controller used to assign lanes to pads two PHYs
are exposed to allow the bricks for PCIe and SATA to be powered up and
down by PCIe and SATA drivers.

Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-11 14:41:06 +02:00
Sachin Kamat ebe629a39e pinctrl: samsung: Group all drivers in a sub-dir
Group all pin control drivers of Samsung platform together in
a sub-directory for easy maintenance.

Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:40 +02:00
Himangi Saraogi aef1d0003d sh-pfc: sh73a0: Introduce the use of devm_regulator_register
This patch moves data allocated using regulator_register to
devm_regulator_register and does away the calls to regulator_unregister.
The sh73a0_pinmux_soc_exit function is no longer needed and is removed.

Signed-off-by: Himangi Saraogi <himangi774@gmail.com>
Acked-by: Julia Lawall <julia.lawall@lip6.fr>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:39 +02:00
Linus Walleij 69b78b8de6 pinctrl: msm: move all qualcomm drivers to subdir
We have four Qualcomm-related pin control drivers, and now there
are drivers coming in for the PMICs on these systems, so let's
create a qcom subdirectory to hold all the Qualcomm stuff.

Acked-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:38 +02:00
Bjorn Andersson 14d40ff8f8 pinctrl: msm: Add msm8960 definitions
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:38 +02:00
Tomasz Figa 2700bc0135 pinctrl: samsung: Allow pin value to be initialized using pinfunc
This patch extends the range of settings configurable via pinfunc API
to cover pin value as well. This allows configuration of default values
of pins, which is useful for pins that are not supposed to be used by
any dedicated driver, but need certain board-specific setting.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:38 +02:00
Tomasz Figa 9a2c1c3b91 pinctrl: samsung: Allow grouping multiple pinmux/pinconf nodes
One of remaining limitations of current pinctrl-samsung driver was
the inability to parse multiple pinmux/pinconf group nodes grouped
inside a single device tree node. It made defining groups of pins for
single purpose, but with different parameters very inconvenient.

This patch implements Tegra-like support for grouping multiple pinctrl
groups inside one device tree node, by completely changing the way
pin groups and functions are parsed from device tree. The code creating
pinctrl maps from DT nodes has been borrowed from pinctrl-tegra, while
the initial creation of groups and functions has been completely
rewritten with following assumptions:
 - each group consists of just one pin and does not depend on data
   from device tree,
 - each function is represented by a device tree child node of the
   pin controller, which in turn can contain multiple child nodes
   for pins that need to have different configuration values.

Device Tree bindings are fully backwards compatible. New functionality
can be used by defining a new pinctrl group consisting of several child
nodes, as on following example:

	sd4_bus8: sd4-bus-width8 {
		part-1 {
			samsung,pins = "gpk0-3", "gpk0-4",
					"gpk0-5", "gpk0-6";
			samsung,pin-function = <3>;
			samsung,pin-pud = <3>;
			samsung,pin-drv = <3>;
		};
		part-2 {
			samsung,pins = "gpk1-3", "gpk1-4",
					"gpk1-5", "gpk1-6";
			samsung,pin-function = <4>;
			samsung,pin-pud = <4>;
			samsung,pin-drv = <3>;
		};
	};

Tested on Exynos4210-Trats board and a custom Exynos4212-based one.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:37 +02:00
Tomasz Figa 2e4a4fda30 pinctrl: exynos: Consolidate irq_chips of GPIO and WKUP EINTs
Handling of irq_chip operations for GPIO and WKUP external interrupts
is mostly the same, with the difference being offset of registers.
However currently the driver has all the code duplicated for both EINT
types, which is undesirable, because changes in irq_chip operations have
to be done to both instances of the same code.

This patch fixes this by creating exynos_irq_chip struct that has normal
irq_chip struct embedded and contain differences between particular EINT
types, which are three register offsets. One instance of code is removed
and the new structure is used instead to fetch necessary data instead of
samsung_pin_ctrl struct used previously.

While at it, the patch removes Exynos-specific fields from
aforementioned structure to improve layering of the driver.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:37 +02:00
Tomasz Figa 6c6ce620e0 pinctrl: samsung: Handle GPIO request and free using pinctrl helpers
This patch adds .request() and .free() operations to gpio_chip of
pinctrl-samsung driver, which call pinctrl request and free helpers to
request and free pinctrl pin along with GPIO pin.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:37 +02:00
Tomasz Figa 18c28caa17 pinctrl: samsung: Decouple direction setting from pinctrl
This patch makes the pinctrl-samsung driver configure GPIO direction on
its own, without using the pinctrl_gpio_direction_*() "helpers". The
rationale behind this change is as follows:
 - pinctrl-samsung does not need translation from GPIO namespace to
   pinctrl namespace to handle GPIO operations - GPIO chip and offset
   therein are enough to calculate necessary offsets and bit masks in
   constant time,
 - the pinctrl_gpio_direction_*() functions do not do anything useful
   other than translating the pin into pinctrl namespace and calling the
   .gpio_set_direction() from pinmux_ops of the controller,
 - the undesirable side effect of using those helpers is losing the
   ability to change GPIO direction in atomic context, because they
   explicitly use a mutex for synchronization,

Results of this patch are:
 - fixed warnings about scheduling while atomic in code that needs to
   set GPIO direction in atomic context (e.g. interrupt handler),
 - reduced overhead of bitbanging drivers that use gpio_direction_*(),
   e.g. i2c-gpio.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:36 +02:00
Sergei Shtylyov 0e93867527 sh-pfc: r8a7791: add CAN pin groups
Add CAN0/1 data/clock pin groups to R8A7791 PFC driver.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:36 +02:00
Eric Ernst ff998356b6 pinctrl: baytrail: Warn if direct IRQ GPIO set to output
For Baytrail, you should never set a GPIO set to direct_irq
to output mode.  When direct_irq_en is set for a GPIO, it is
tied directly to an APIC internally, and making the pad output
does not make any sense. Assert a WARN() in the event this happens.

Signed-off-by: Eric Ernst <eric.ernst@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:35 +02:00
Rickard Strandqvist 1f978217a0 pinctrl: pinctrl-st.c: Cleaning up values that are never used
Remove variable that are never used

This was found using a static code analysis program called cppcheck.

Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:35 +02:00
Rickard Strandqvist bf4cef6c70 pinctrl: pinctrl-single.c: Cleaning up wrong format string usage
%d in format string used, but the type is unsigned int

This was found using a static code analysis program called cppcheck

Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:35 +02:00
Rickard Strandqvist 719e231bed pinctrl: pinctrl-adi2.c: Cleaning up wrong format string usage
%d in format string used, but the type is unsigned int

This was found using a static code analysis program called cppcheck

Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:34 +02:00
Rickard Strandqvist 849bfe0637 pinctrl: pinctrl-single.c: Cleaning up values that are never used
Remove variable that are never used

This was found using a static code analysis program called cppcheck.

Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:34 +02:00
Rickard Strandqvist 445d20260b pinctrl: pinctrl-at91.c: Cleaning up values that are never used
Remove variable that are never used

This was found using a static code analysis program called cppcheck.

Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:33 +02:00
Rickard Strandqvist 8b0c107ce0 pinctrl: pinctrl-st.c: Cleaning up if unsigned is less than zero
Remove checking if a unsigned is less than zero

This was found using a static code analysis program called cppcheck.

Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:33 +02:00
Rickard Strandqvist 5aa498b954 pinctrl: pinctrl-imx1-core.c: Cleaning up if unsigned is less than zero
Remove checking if a unsigned is less than zero

This was found using a static code analysis program called cppcheck.

Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:33 +02:00
Rickard Strandqvist 9eedfd688c pinctrl: pinctrl-imx.c: Cleaning up if unsigned is less than zero
Remove checking if a unsigned is less than zero

This was found using a static code analysis program called cppcheck.

Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:32 +02:00
Rickard Strandqvist ca7162add9 pinctrl: pinctrl-at91.c: Cleaning up if unsigned is less than zero
Remove checking if a unsigned is less than zero

This was found using a static code analysis program called cppcheck.

Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:32 +02:00
David PARIS 8708ebca74 pinctrl: st: add IRQCHIP_SKIP_SET_WAKE flag
no .irq_set_wake API is available for pinctrl-st driver.
Add the IRQCHIP_SKIP_SET_WAKE flag to inform irq handler
not to call this API.

Signed-off-by: David Paris <david.paris@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:31 +02:00
Sachin Kamat 776667a809 pinctrl: bcm281xx: Staticize bcm281xx_pinctrl_probe
bcm281xx_pinctrl_probe is local to this file. Make it static.

Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:31 +02:00
Andy Gross b831a15e2b pinctrl: qcom: Add BUS_HOLD pin bias
This patch adds the BUS_HOLD (Keeper) bias option for pins.

Signed-off-by: Andy Gross <agross@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:31 +02:00
Chen-Yu Tsai d22bf40f46 pinctrl: sunxi: Add A23 R_PIO controller support
The A23 has a R_PIO pin controller, similar to the one found on the A31 SoC.
Add support for the pins controlled by the R_PIO controller.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:30 +02:00
Chen-Yu Tsai 4c821d1c93 pinctrl: sunxi: Add A23 PIO controller support
The A23 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:30 +02:00
Maxime Ripard d9ff081d91 pinctrl: sunxi: Remove PINCTRL_SUNXI
The PINCTRL_SUNXI configuration was kept only to deal with the introduction of
per-machine symbols and the various pintrl drivers through different tree.

Now that it's not useful anymore, we can just remove it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:29 +02:00