Commit Graph

6 Commits

Author SHA1 Message Date
Maxime Ripard a0d72094f0 pinctrl: sunxi: add of_xlate function
Since the pin controller of sunxi chips is represented as a
single bank in the driver.

Since this is neither convenient nor represented that way in the
datasheets, define a custom of_xlate function with the layout
<bank pin flag>

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-05 17:32:29 +01:00
Maxime Ripard 9f5b6b30f9 ARM: pinctrl: sunxi: Add the pinctrl pin set for Allwinner A10
Since the Allwinner SoCs variants don't have the same set of pins to
handle, we need to declare the pin ranges available.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-01 10:45:34 +01:00
Maxime Ripard ae1575f711 pinctrl: sunxi: Document sun5i pins functions
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-01 10:44:21 +01:00
Maxime Ripard 08e9e614ca ARM: sunxi: gpio: Add Allwinner SoCs GPIO drivers
The IP responsible for the muxing on the Allwinner SoCs are also
handling the GPIOs on the system. This patch adds the needed driver that
relies on the pinctrl driver for most of its operations.

The number of pins available for GPIOs operations are already declared
in the pinctrl driver, we only need to probe a generic driver to handle
the banks available for each SoC.

This driver has been tested on a A13-Olinuxino.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-29 23:37:16 +01:00
Maxime Ripard eaa3d8489d ARM: pinctrl: sunxi: Add the pinctrl pin set for sun5i
Since the Allwinner SoCs variants don't have the same set of pins to
handle, we need to declare the pin ranges available.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-22 13:51:35 +01:00
Maxime Ripard 0e37f88d9a ARM: sunxi: Add pinctrl driver for Allwinner SoCs
The Allwinner SoCs have an IP module that handle both the muxing and the
GPIOs.

This IP has 8 banks of 32 bits, with a number of pins actually useful
for each of these banks varying from one to another, and depending on
the SoC used on the board.

This driver only implements the pinctrl part, the gpio part will come
eventually.

Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-22 13:51:15 +01:00