These lines just have unsigned gpio rather than unsigned int gpio.
I changed it to suit the coding style. Michael Buesch told me to
send this to the MIPS tree.
Signed-off-by: Hugh Sipière <hgsipiere@gmail.com>
Acked-by: Michael Buesch <m@bues.ch>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13460/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This makes the driver use the data pointer added to the gpio_chip
to store a pointer to the state container instead of relying on
container_of().
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Michael Buesch <m@bues.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
this remove all reference to gpio_remove retval in all driver
except pinctrl and gpio. the same thing is done for gpio and
pinctrl in two different patches.
Signed-off-by: Abdoulaye Berthe <berthe.ab@gmail.com>
Acked-by: Michael Büsch <m@bues.ch>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Synchronize with 'net' in order to sort out some l2tp, wireless, and
ipv6 GRE fixes that will be built on top of in 'net-next'.
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch unregisters the gpio chip before ssb gets unloaded.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
The old bcm47xx gpio code had support for gpio_to_irq, but the new
code did not provide this function, but returned -ENXIO all the time.
This patch adds the missing function.
arch/mips/bcm47xx/wgt634u.c calls gpio_to_irq() and got the correct irq
number with the old gpio handling code. With this patch the code in
wgt634u.c should work again. I do not have a wgt634u to test this.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Register a GPIO driver to access the GPIOs provided by the chip.
The GPIOs of the SoC should always start at 0 and the other GPIOs could
start at a random position. There is just one SoC in a system and when
they start at 0 the number is predictable.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: http://patchwork.linux-mips.org/patch/4591
Acked-by: Florian Fainelli <florian@openwrt.org>
Hugh Sipière