Commit Graph

88 Commits

Author SHA1 Message Date
Uwe Kleine-König 692d8328e8 clk: don't use __initconst for non-const arrays
The statement

	static const char *name[];

defines a modifiable array of pointers to constant chars. That is

	*name[0] = 'f';

is forbidden, but

	name[0] = "f";

is not. So marking an array that is defined as above with __initconst is
wrong. Either an additional const must be added such that the whole
definition reads:

	static const char *const name[] __initconst;

or where this is not possible __initdata must be used.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-04-12 17:18:27 -07:00
Fabian Frederick f375573c96 clk: constify of_device_id array
of_device_id is always used as const.
(See driver.of_match_table and open firmware functions)

__initdata updated to __initconst for
static const struct of_device_id ti_clkdm_match_table[]

Signed-off-by: Fabian Frederick <fabf@skynet.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-01 10:59:27 -07:00
Michael Turquette c77662a4df Merge branch 'for-4.1-clk-ti' of github.com:t-kristo/linux-pm into clk-next 2015-03-24 16:47:43 -07:00
Tony Lindgren 9089848d9a clk: ti: Implement FAPLL set_rate for the PLL
Since we have a fractional divider for the synthesizer, just implement
a simple multiply logic for the PLL.

It seems the PLL divider needs to have also the multiplier set for the PLL
to lock. At least I have not yet figured out if divided rates are doable.

So let's just ignore the PLL divider for now as the synthesizer has both
integer and fractional dividers so we don't even need to use the PLL
divider for the rates we know work with PLL locking.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2015-03-24 20:26:14 +02:00
Tony Lindgren cafeb002cf clk: ti: Implement FAPLL set_rate for the synthesizer
We can pretty much get any rate out of the FAPLL because of the fractional
divider. Let's first try just adjusting the post divider, and if that is
not enough, then reprogram both the fractional divider and the post divider.

Let's also add a define for the fixed SYNTH_PHASE_K instead of using 8.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2015-03-24 20:26:05 +02:00
Tony Lindgren 33ca29c99e clk: ti: Fix FAPLL recalc_rate for rounding errors
We need to round the calculated value to have it match the requested rate.

While at it, let's fix a typo and use a define for SYNTH_MAX_DIV_M as we
will need it in later patches for set_rate.

And let's remove two unused includes.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2015-03-24 20:26:05 +02:00
Suman Anna 712f7d64f0 clk: ti: DRA7: Add timer_sys_ck aliases for Timers 13 through 16
The OMAP DMTimer API, omap_dm_timer_set_source(), uses the clock name
timer_sys_ck for setting a timer's clock source for the source index
OMAP_TIMER_SRC_SYS_CLK. There is currently no clock alias data for
the Timers 13 through 16 for this clock name, so add the same.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2015-03-24 20:23:51 +02:00
Suman Anna d4295be387 clk: ti: DRA7: Correct timer_sys_ck clock aliases for Timers
The OMAP DMTimer API, omap_dm_timer_set_source(), can set the parent
of a timer node using 3 different values that use fixed parent names
for the clocks. The parent name, timer_sys_ck, is used for setting the
parent when used with the source index OMAP_TIMER_SRC_SYS_CLK. This
should point to the TIMER_SYS_CLK and not the SYSCLKIN2, so correct
the clock aliases appropriately. SYSCLKIN2 is not a mandatory clock
input.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2015-03-24 20:23:50 +02:00
Suman Anna 03ff41a938 clk: ti: OMAP5: Correct the DT clock aliases for timers
The DT clock aliases for Timers use the legacy (non-DT) device
names and a source clock named sys_ck. OMAP5 is DT-boot only,
so correct the DT clock aliases to use the DT device names
instead. Also, the source clock name is corrected from 'sys_ck'
to 'timer_sys_ck', the name used by the OMAP dmtimer driver.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2015-03-24 20:23:50 +02:00
Suman Anna 2ff8d75c23 clk: ti: OMAP4: Remove the legacy timer DT clock aliases
The DT clock aliases for timers using the legacy OMAP timer
device names have been cleaned up. These device names reflect
the names used in legacy boot, and are no longer applicable
as OMAP4 is DT boot only now.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2015-03-24 20:23:50 +02:00
Peter Ujfalusi c8d3829212 clk: ti: clk-3xxx-legacy: Correct McBSP related clock aliases
Correct the McBSP2/4 ick mapping (they were 2->4 and 4->2).
Add missing mcbsp clock aliases.
Collect the McBSP clock definition in one location at the same time.

Fixes the following warning on boot:
[    0.307739] omap_hwmod: mcbsp2: _wait_target_ready failed: -16
[    0.307769] omap_hwmod: mcbsp2: cannot be enabled for reset (3)

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2015-03-24 20:23:50 +02:00
Peter Ujfalusi f757d1b047 clk: ti: clk-3xxx: Correct McBSP related DT clock definitions
In DT boot we do not have devices named as omap-mcbsp.X.
Correct the McBSP2/4 ick mapping (they were 2->4 and 4->2).
Collect the McBSP clock definition in one location at the same time.

Fixes the following warning on boot:
[    0.307739] omap_hwmod: mcbsp2: _wait_target_ready failed: -16
[    0.307769] omap_hwmod: mcbsp2: cannot be enabled for reset (3)

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2015-03-24 20:23:50 +02:00
Tero Kristo c807dbedb5 clk: ti: fix ti_clk_get_reg_addr error handling
There is a case where NULL can be a valid return value for
ti_clk_get_reg_addr, specifically the case where both the provider index
and register offsets are zero. In this case, the current error checking
against a NULL pointer will fail. Thus, change the API to return a
ERR_PTR value in an error case, and change all the users of this API to
check against IS_ERR instead.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
2015-03-24 20:23:36 +02:00
Tony Lindgren 03208cc69f clk: ti: Fix FAPLL parent enable bit handling
Commit 163152cbbe ("clk: ti: Add support for FAPLL on dm816x")
added basic support for the FAPLL on dm818x, but has a bug for the
parent PLL enable bit. The FAPLL_MAIN_PLLEN is defined as BIT(3)
but the code is doing a shift on it.

This means the parent PLL won't get disabled even if all it's child
synthesizers are disabled.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-25 12:06:29 -08:00
Arnd Bergmann 6793a30a06 clk: omap: compile legacy omap3 clocks conditionally
The 'ARM: OMAP3: legacy clock data move under clk driver' patch series
causes build errors when CONFIG_OMAP3 is not set:

drivers/clk/ti/dpll.c: In function 'ti_clk_register_dpll':
drivers/clk/ti/dpll.c:199:31: error: 'omap3_dpll_ck_ops' undeclared (first use in this function)
  const struct clk_ops *ops = &omap3_dpll_ck_ops;
                               ^
drivers/clk/ti/dpll.c:199:31: note: each undeclared identifier is reported only once for each function it appears in
drivers/clk/ti/dpll.c:259:10: error: 'omap3_dpll_per_ck_ops' undeclared (first use in this function)
   ops = &omap3_dpll_per_ck_ops;
          ^

drivers/built-in.o: In function `ti_clk_register_gate':
drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_omap3430es2_dss_usbhost_wait'
drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_am35xx_ipss_module_wait'
-in.o: In function `ti_clk_register_interface':
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_omap3430es2_iclk_hsotgusb_wait'
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_omap3430es2_iclk_dss_usbhost_wait'
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_omap3430es2_iclk_ssi_wait'
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_am35xx_ipss_wait'
drivers/built-in.o: In function `ti_clk_register_composite':
:(.text+0x3da768): undefined reference to `ti_clk_build_component_gate'

In order to fix that problem, this patch makes the omap3 legacy code
compiled only when both CONFIG_OMAP3 and CONFIG_ATAGS are set.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-03 11:06:11 -08:00
Michael Turquette fe76756052 Merge branch 'clk-omap-legacy' into clk-next
Conflicts:
	arch/arm/mach-omap2/cclock3xxx_data.c
2015-02-02 14:23:33 -08:00
Tero Kristo 74807dffcd clk: ti: add omap3 legacy clock data
Introduces omap3 legacy clock data under clock driver. The clock data
is also in new format, which makes it possible to get rid of the
clk-private.h header. This patch also introduces SoC specific init
functions that shall be called from the low level init.

The data format used in this file has two possible evolution paths;
it can either be removed completely once no longer needed, or it will
be possible to retain the format and modify the TI clock driver to be
a loadable module at some point. The actual path to be followed
will be decided later.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:55:19 -08:00
Tero Kristo b26bcf9be6 clk: ti: composite: add support for legacy composite clock init
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:55:15 -08:00
Tero Kristo ed405a2350 clk: ti: dpll: add support for legacy DPLL init
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:55:09 -08:00
Tero Kristo d96f774b25 clk: ti: divider: add support for legacy divider init
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:55:05 -08:00
Tero Kristo 06524fa428 clk: ti: interface: add support for legacy interface clock init
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this. The interface clock descriptor
itself is overloading the gate clock descriptor, thus it needs to
be called from the gate setup.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:55:00 -08:00
Tero Kristo f187616b36 clk: ti: gate: add support for legacy gate init
Legacy clock data is initialialized slightly differently compared to
DT clocks, thus add support for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:54:54 -08:00
Tero Kristo 7c18a65cb5 clk: ti: mux: add support for legacy mux init
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:54:49 -08:00
Tero Kristo c82f8957b4 clk: ti: add core support for initializing legacy clocks
Legacy clock data for OMAP3 is being moved under clock driver, thus
base support for this is needed. This patch adds basic definitions for
clock init descriptors and core infrastructure for initialization,
which will be called from the OMAP3 clock init.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:50:09 -08:00
Stephen Boyd e387088a03 clk: ti: Drop use of clk-private.h
These modules don't need to include clk-private.h. Replace the
include with clk.h because these modules are clock consumers and
also include clk-provider.h in clk/ti.h because struct
clk_hw_omap has a struct clk_hw embedded in it.

Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27 11:58:54 -08:00
Tony Lindgren 1a34275d34 clk: ti: Initialize clocks for dm816x
The clocks on ti81xx are not compatible with omap3. On dm816x
the clock source is a FAPLL (Flying Adder PLL), and on dm814x
there seems to be an APLL (All Digital PLL).

Let's fix up things for dm816x in preparation for adding the
FAPLL support. As we already have a dummy ti81xx_dt_clk_init()
in place, let's use that for now to avoid adding a dependency
to the omap patches.

Later on if somebody adds dm814x support we can split the
ti81xx_dt_clk_init() clock init function as needed.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-20 10:09:08 -08:00
Tony Lindgren 163152cbbe clk: ti: Add support for FAPLL on dm816x
On dm816x the clocks are sourced from a FAPLL (Flying Adder PLL)
that does not seem to be used on the other omap variants.

There are four instances of the FAPLL on dm816x that each have three
to seven child synthesizers.

I've set up the FAPLL as a single fapll.c driver. Later on we could
potentially have the PLL code generic. To do that, we would have to
consider the following:

1. Setting the PLL to bypass mode also sets the child synthesizers
   into bypass mode. As the bypass rate can also be generated by
   the PLL in regular mode, there's no way for the child synthesizers
   to detect the bypass mode based on the parent clock rate.

2. The PLL registers control the power for each of the child
   syntheriser.

Note that the clocks are currently still missing the set_rate
implementation so things are still running based on the bootloader
values. That's OK for now as most of the outputs have dividers and
those can be set using the existing TI component clock code.

I have verified that the extclk rates are correct for a few clocks,
so adding the set_rate support should be fairly trivial later on.

This code is partially based on the TI81XX-LINUX-PSP-04.04.00.02
patches published at:

http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-20 10:09:07 -08:00
Tero Kristo 2e1a7b014f ARM: OMAP3+: DPLL: use determine_rate() and set_rate_and_parent()
Currently, DPLLs are hiding the gory details of switching parent
within set_rate, which confuses the common clock code and is wrong.
Fixed by applying the new determine_rate() and set_rate_and_parent()
functionality to any clock-ops previously using the broken approach.
This patch also removes the broken legacy code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-11-13 09:26:45 -07:00
Mike Turquette 82de1bc86c Merge branch 'for-v3.18/ti-clk-driver' of github.com:t-kristo/linux-pm into clk-next 2014-09-29 23:38:59 -07:00
Peter Ujfalusi 04ed831f22 clk: ti: dra7-atl-clock: Mark the device as pm_runtime_irq_safe
It is safe to call the pm sync calls in interrupt context in this driver.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-09-29 11:51:14 +03:00
Behan Webster e8627a9ec3 clk: ti: LLVMLinux: Move __init outside of type definition
As written, the __init for ti_clk_get_div_table is in the middle of the return
type.

The gcc documentation indicates that section attributes should be added to the
end of the function declaration:

  extern void foobar (void) __attribute__ ((section ("bar")));

However gcc seems to be very permissive with where attributes can be placed.
clang on the other hand isn't so permissive, and fails if you put the section
definition in the middle of the return type:

drivers/clk/ti/divider.c:298:28: error: expected ';' after struct
static struct clk_div_table
                           ^
                           ;
drivers/clk/ti/divider.c:298:1: warning: 'static' ignored on this
      declaration [-Wmissing-declarations]
static struct clk_div_table
^
drivers/clk/ti/divider.c:299:9: error: type specifier missing,
      defaults to 'int' [-Werror,-Wimplicit-int]
__init *ti_clk_get_div_table(struct device_node *node)
~~~~~~  ^
drivers/clk/ti/divider.c:345:9: warning: incompatible pointer types
      returning 'struct clk_div_table *' from a function with result type 'int *' [-Wincompatible-pointer-types]
        return table;
               ^~~~~
drivers/clk/ti/divider.c:419:9: warning: incompatible pointer types
      assigning to 'const struct clk_div_table *' from 'int *' [-Wincompatible-pointer-types]
        *table = ti_clk_get_div_table(node);
               ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~
3 warnings and 2 errors generated.

By convention, most of the kernel code puts section attributes between the
return type and function name. In the case where the return type is a pointer,
it's important to place the '*' on left of the __init.

This updated code works for both gcc and clang.

Signed-off-by: Behan Webster <behanw@converseincode.com>
Reviewed-by: Mark Charlebois <charlebm@gmail.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-09-29 11:51:14 +03:00
Sebastian Andrzej Siewior 319f1276f9 clk: ti: consider the fact that of_clk_get() might return an error
I "forgot" to update the dtb and the kernel crashed:
|Unable to handle kernel NULL pointer dereference at virtual address 0000002e
|PC is at __clk_get_flags+0x4/0xc
|LR is at ti_dt_clockdomains_setup+0x70/0xe8

because I did not have the clock nodes. of_clk_get() returns an error
pointer which is not checked here.

Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-09-29 11:51:13 +03:00
Tero Kristo 73b5d5f711 clk: ti: dra7-atl-clock: fix a memory leak
of_clk_add_provider makes an internal copy of the parent_names property
while its called, thus it is no longer needed after this call and can
be freed.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
2014-09-29 11:51:13 +03:00
Tero Kristo c08ee14cc6 clk: ti: change clock init to use generic of_clk_init
Previously, the TI clock driver initialized all the clocks hierarchically
under each separate clock provider node. Now, each clock that requires
IO access will instead check their parent node to find out which IO range
to use.

This patch allows the TI clock driver to use a few new features provided
by the generic of_clk_init, and also allows registration of clock nodes
outside the clock hierarchy (for example, any external clocks.)

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Jyri Sarha <jsarha@ti.com>
Cc: Stefan Assmann <sassmann@kpanic.de>
Acked-by: Tony Lindgren <tony@atomide.com>
2014-09-29 11:51:13 +03:00
Kiran Padwal 59c0621d4d clk: Remove .owner field for driver
There is no need to init .owner field.

Based on the patch from Peter Griffin <peter.griffin@linaro.org>
"mmc: remove .owner field for drivers using module_platform_driver"

This patch removes the superflous .owner field for drivers which
use the module_platform_driver API, as this is overriden in
platform_driver_register anyway."

Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-25 17:43:31 -07:00
Nishanth Menon 20411dad75 clk: ti: dra7-atl: Provide error check for incoming parameters in set_rate
Check for valid parameters in check rate. Else, we end up getting
errors.

This occurs as part of the inital clock tree update of child clock
nodes where new_rate could be 0 for non functional clocks.

Fixes: 9ac33b0ce8 (" CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)")
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-08-21 18:04:16 +03:00
Nishanth Menon 2f10325176 clk: ti: divider: Provide error check for incoming parameters in set_rate
Check for valid parameters in check rate. Else, we end up getting errors
like:
[    0.000000] Division by zero in kernel.
[    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.17.0-rc1 #1
[    0.000000] [<c0015160>] (unwind_backtrace) from [<c0011978>] (show_stack+0x10/0x14)
[    0.000000] [<c0011978>] (show_stack) from [<c055f5f4>] (dump_stack+0x78/0x94)
[    0.000000] [<c055f5f4>] (dump_stack) from [<c02e17cc>] (Ldiv0+0x8/0x10)
[    0.000000] [<c02e17cc>] (Ldiv0) from [<c047d228>] (ti_clk_divider_set_rate+0x14/0x14c)
[    0.000000] [<c047d228>] (ti_clk_divider_set_rate) from [<c047a938>] (clk_change_rate+0x138/0x180)
[    0.000000] [<c047a938>] (clk_change_rate) from [<c047a908>] (clk_change_rate+0x108/0x180)

This occurs as part of the inital clock tree update of child clock nodes
where new_rate could be 0 for non functional clocks.

Fixes: b4761198bf ("CLK: ti: add support for ti divider-clock")
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-08-21 18:04:16 +03:00
Linus Torvalds e4ca4308c0 The clock framework changes for 3.17 are mostly additions of new clock
drivers and fixes/enhancements to existing clock drivers. There are also
 some non-critical fixes and improvements to the framework core.
 
 Changes to the clock framework core include:
 * improvements to printks on errors
 * flattening the previously hierarchal structure of per-clock entries
   in debugfs
 * allow per-clock debugfs entries that are specific to a particular
   clock driver
 * configure initial clock parent and/or initial clock rate from Device
   Tree
 * several feature enhancements to the composite clock type
 * misc fixes
 
 New clock drivers added include:
 * TI Palmas PMIC
 * Allwinner A23 SoC
 * Qualcomm APQ8084 and IPQ8064 SoCs
 * Rockchip rk3188, rk3066 and rk3288 SoCs
 * STMicroelectronics STiH407 SoC
 * Cirrus Logic CLPS711X SoC
 
 Many fixes, feature enhancements and further clock tree support for
 existing clock drivers also were merged, such as Samsung's "ARMCLK down"
 power saving feature for their Exynos4 & Exynos5 SoCs.
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Merge tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux

Pull clock framework updates from Mike Turquette:
 "The clock framework changes for 3.17 are mostly additions of new clock
  drivers and fixes/enhancements to existing clock drivers.  There are
  also some non-critical fixes and improvements to the framework core.

  Changes to the clock framework core include:
   - improvements to printks on errors
   - flattening the previously hierarchal structure of per-clock entries
     in debugfs
   - allow per-clock debugfs entries that are specific to a particular
     clock driver
   - configure initial clock parent and/or initial clock rate from
     Device Tree
   - several feature enhancements to the composite clock type
   - misc fixes

  New clock drivers added include:
   - TI Palmas PMIC
   - Allwinner A23 SoC
   - Qualcomm APQ8084 and IPQ8064 SoCs
   - Rockchip rk3188, rk3066 and rk3288 SoCs
   - STMicroelectronics STiH407 SoC
   - Cirrus Logic CLPS711X SoC

  Many fixes, feature enhancements and further clock tree support for
  existing clock drivers also were merged, such as Samsung's "ARMCLK
  down" power saving feature for their Exynos4 & Exynos5 SoCs"

* tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: Add missing of_clk_set_defaults export
  clk: checking wrong variable in __set_clk_parents()
  clk: Propagate any error return from debug_init()
  clk: clps711x: Add DT bindings documentation
  clk: Add CLPS711X clk driver
  clk: st: Use round to closest divider flag
  clk: st: Update frequency tables for fs660c32 and fs432c65
  clk: st: STiH407: Support for clockgenA9
  clk: st: STiH407: Support for clockgenD0/D2/D3
  clk: st: STiH407: Support for clockgenC0
  clk: st: Add quadfs reset handling
  clk: st: Add polarity bit indication
  clk: st: STiH407: Support for clockgenA0
  clk: st: STiH407: Support for A9 MUX Clocks
  clk: st: STiH407: Support for Flexgen Clocks
  clk: st: Adds Flexgen clock binding
  clk: st: Remove uncessary (void *) cast
  clk: st: use static const for clkgen_pll_data tables
  clk: st: use static const for stm_fs tables
  clk: st: Update ST clock binding documentation
  ...
2014-08-04 11:44:20 -07:00
Peter Ujfalusi a74c52def9 clk: ti: clk-7xx: Correct ABE DPLL configuration
ABE DPLL frequency need to be lowered from 361267200
to 180633600 to facilitate the ATL requironments.
The dpll_abe_m2x2_ck clock need to be set to double
of ABE DPLL rate in order to have correct clocks
for audio.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-31 08:36:58 -07:00
Mike Turquette 07761baff0 Merge branch 'for-v3.17/ti-clk-driver' of github.com:t-kristo/linux-pm into clk-next-ti 2014-07-25 15:37:40 -07:00
Roger Quadros 94e72ae5db CLK: ti: dra7: Initialize USB_DPLL
USB_DPLL must be initialized and locked at boot so that
USB modules can work.

Also program USB_DLL_M2 output to half rate.

CC: Mike Turquette <mturquette@linaro.org>
CC: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-07-02 17:08:26 +03:00
Tomi Valkeinen 7d5fc85d96 clk: ti: set CLK_SET_RATE_NO_REPARENT for ti,mux-clock
When setting the rate of a clock, by default the clock framework will
change the parent of the clock to the most suitable one in
__clk_mux_determine_rate() (most suitable by looking at the clock rate).

This is a rather dangerous default, and causes problems on AM43x when
using display and ethernet. There are multiple ways to select the clock
muxes on AM43x, and some of those clock paths have the same source
clocks for display and ethernet. When changing the clock rate for the
display subsystem, the clock framework decides to change the display mux
from the dedicated display PLL to a shared PLL which is used by the
ethernet, and then changes the rate of the shared PLL, breaking the
ethernet.

As I don't think there ever is a case where we want the clock framework
to automatically change the parent clock of a clock mux, this patch sets
the CLK_SET_RATE_NO_REPARENT for all ti,mux-clocks.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-06-19 14:52:32 +03:00
Roger Quadros 32cff42d0d clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled
Define ti_clk_register_dpll_x2() and of_ti_am3_dpll_x2_setup() if
AM43XX is defined.

Fixes the below boot issue.

[    2.157258] gpmc_l3_clk not enabled
[    2.161194] gpmc_l3_clk not enabled
[    2.164896] Division by zero in kernel.
[    2.169055] CPU: 0 PID: 321 Comm: kworker/u2:2 Tainted: G        W     3.16.0-rc1-00008-g4c0e520 #273
[    2.178880] Workqueue: deferwq deferred_probe_work_func
[    2.184459] [<c001477c>] (unwind_backtrace) from [<c001187c>] (show_stack+0x10/0x14)
[    2.192752] [<c001187c>] (show_stack) from [<c0530f28>] (dump_stack+0x80/0x9c)
[    2.200486] [<c0530f28>] (dump_stack) from [<c02c867c>] (Ldiv0+0x8/0x10)
[    2.207678] [<c02c867c>] (Ldiv0) from [<c0022da0>] (gpmc_calc_divider+0x24/0x40)
[    2.215490] [<c0022da0>] (gpmc_calc_divider) from [<c0022e20>] (gpmc_cs_set_timings+0x18/0x474)
[    2.224783] [<c0022e20>] (gpmc_cs_set_timings) from [<c003069c>] (gpmc_nand_init+0x74/0x1a8)
[    2.233791] [<c003069c>] (gpmc_nand_init) from [<c0024668>] (gpmc_probe+0x52c/0x874)
[    2.242089] [<c0024668>] (gpmc_probe) from [<c0349218>] (platform_drv_probe+0x18/0x48)
[    2.250534] [<c0349218>] (platform_drv_probe) from [<c0347d88>] (driver_probe_device+0x104/0x22c)
[    2.259988] [<c0347d88>] (driver_probe_device) from [<c03464dc>] (bus_for_each_drv+0x44/0x8c)
[    2.269087] [<c03464dc>] (bus_for_each_drv) from [<c0347c4c>] (device_attach+0x74/0x8c)
[    2.277620] [<c0347c4c>] (device_attach) from [<c0347380>] (bus_probe_device+0x88/0xb0)
[    2.286074] [<c0347380>] (bus_probe_device) from [<c0347768>] (deferred_probe_work_func+0x60/0x90)
[    2.295611] [<c0347768>] (deferred_probe_work_func) from [<c004ef50>] (process_one_work+0x1b4/0x4bc)
[    2.305288] [<c004ef50>] (process_one_work) from [<c004f3d4>] (worker_thread+0x148/0x550)
[    2.313954] [<c004f3d4>] (worker_thread) from [<c0055a48>] (kthread+0xc8/0xe4)
[    2.321628] [<c0055a48>] (kthread) from [<c000e648>] (ret_from_fork+0x14/0x2c)

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-06-19 14:52:31 +03:00
Julia Lawall 8d2f9e8eca clk: ti: dra7: return error code in failure case
Add a returned error code in the MAX_APLL_WAIT_TRIES case.  Remove the
updating of the return variable r to 0 if MAX_APLL_WAIT_TRIES is not yet
reached, because r is already 0 at this point.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-06-19 14:52:31 +03:00
Dan Carpenter 6c7ee8905d clk: ti: apll: not allocating enough data
There is a cut and paste bug here which will lead to memory corruption
because we don't allocate enough data.

Fixes: 4d008589e2 ('CLK: TI: APLL: add support for omap2 aplls')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-06-19 14:52:31 +03:00
Linus Torvalds dd1845af24 This pull request contains the second half the of the clk changes for
3.16. They are simply fixes and code refactoring for the OMAP clock
 drivers. The sunxi clock driver changes include splitting out the one
 mega-driver into several smaller pieces and adding support for the A31
 SoC clocks.
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Merge tag 'clk-for-linus-3.16-part2' of git://git.linaro.org/people/mike.turquette/linux

Pull more clock framework updates from Mike Turquette:
 "This contains the second half the of the clk changes for 3.16.

  They are simply fixes and code refactoring for the OMAP clock drivers.
  The sunxi clock driver changes include splitting out the one
  mega-driver into several smaller pieces and adding support for the A31
  SoC clocks"

* tag 'clk-for-linus-3.16-part2' of git://git.linaro.org/people/mike.turquette/linux: (25 commits)
  clk: sunxi: document PRCM clock compatible strings
  clk: sunxi: add PRCM (Power/Reset/Clock Management) clks support
  clk: sun6i: Protect SDRAM gating bit
  clk: sun6i: Protect CPU clock
  clk: sunxi: Rework clock protection code
  clk: sunxi: Move the GMAC clock to a file of its own
  clk: sunxi: Move the 24M oscillator to a file of its own
  clk: sunxi: Remove calls to clk_put
  clk: sunxi: document new A31 USB clock compatible
  clk: sunxi: Implement A31 USB clock
  ARM: dts: OMAP5/DRA7: use omap5-mpu-dpll-clock capable of dealing with higher frequencies
  CLK: TI: dpll: support OMAP5 MPU DPLL that need special handling for higher frequencies
  ARM: OMAP5+: dpll: support Duty Cycle Correction(DCC)
  CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck
  CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)
  dt:/bindings: DRA7 ATL (Audio Tracking Logic) clock bindings
  ARM: dts: dra7xx-clocks: Correct name for atl clkin3 clock
  CLK: TI: gate: add composite interface clock to OMAP2 only build
  ARM: OMAP2: clock: add DT boot support for cpufreq_ck
  CLK: TI: OMAP2: add clock init support
  ...
2014-06-15 16:02:20 -10:00
Linus Torvalds f9da455b93 Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next
Pull networking updates from David Miller:

 1) Seccomp BPF filters can now be JIT'd, from Alexei Starovoitov.

 2) Multiqueue support in xen-netback and xen-netfront, from Andrew J
    Benniston.

 3) Allow tweaking of aggregation settings in cdc_ncm driver, from Bjørn
    Mork.

 4) BPF now has a "random" opcode, from Chema Gonzalez.

 5) Add more BPF documentation and improve test framework, from Daniel
    Borkmann.

 6) Support TCP fastopen over ipv6, from Daniel Lee.

 7) Add software TSO helper functions and use them to support software
    TSO in mvneta and mv643xx_eth drivers.  From Ezequiel Garcia.

 8) Support software TSO in fec driver too, from Nimrod Andy.

 9) Add Broadcom SYSTEMPORT driver, from Florian Fainelli.

10) Handle broadcasts more gracefully over macvlan when there are large
    numbers of interfaces configured, from Herbert Xu.

11) Allow more control over fwmark used for non-socket based responses,
    from Lorenzo Colitti.

12) Do TCP congestion window limiting based upon measurements, from Neal
    Cardwell.

13) Support busy polling in SCTP, from Neal Horman.

14) Allow RSS key to be configured via ethtool, from Venkata Duvvuru.

15) Bridge promisc mode handling improvements from Vlad Yasevich.

16) Don't use inetpeer entries to implement ID generation any more, it
    performs poorly, from Eric Dumazet.

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1522 commits)
  rtnetlink: fix userspace API breakage for iproute2 < v3.9.0
  tcp: fixing TLP's FIN recovery
  net: fec: Add software TSO support
  net: fec: Add Scatter/gather support
  net: fec: Increase buffer descriptor entry number
  net: fec: Factorize feature setting
  net: fec: Enable IP header hardware checksum
  net: fec: Factorize the .xmit transmit function
  bridge: fix compile error when compiling without IPv6 support
  bridge: fix smatch warning / potential null pointer dereference
  via-rhine: fix full-duplex with autoneg disable
  bnx2x: Enlarge the dorq threshold for VFs
  bnx2x: Check for UNDI in uncommon branch
  bnx2x: Fix 1G-baseT link
  bnx2x: Fix link for KR with swapped polarity lane
  sctp: Fix sk_ack_backlog wrap-around problem
  net/core: Add VF link state control policy
  net/fsl: xgmac_mdio is dependent on OF_MDIO
  net/fsl: Make xgmac_mdio read error message useful
  net_sched: drr: warn when qdisc is not work conserving
  ...
2014-06-12 14:27:40 -07:00
Mike Turquette 3f6eec9969 Merge branch 'for-v3.16/ti-clk-drv' of github.com:t-kristo/linux-pm into clk-next 2014-06-10 16:53:25 -07:00
Nishanth Menon b4be018921 CLK: TI: dpll: support OMAP5 MPU DPLL that need special handling for higher frequencies
MPU DPLL on OMAP5, DRA75x, DRA72x has a limitation on the maximum
frequency it can be locked at. Duty Cycle Correction circuit is used
to recover a correct duty cycle for achieving higher frequencies
(hardware internally switches output to M3 output(CLKOUTHIF) from M2
output (CLKOUT)).

So provide support to setup required data to handle Duty cycle by
the setting up the minimum frequency for DPLL. 1.4GHz is common
for all these devices and is based on Technical Reference Manual
information for OMAP5432((SWPU282U) chapter 3.6.3.3.1 "DPLLs Output
Clocks Parameters", and equivalent information from DRA75x, DRA72x
documentation(SPRUHP2E, SPRUHI2P).

Signed-off-by: Nishanth Menon <nm@ti.com>
[t-kristo@ti.com: updated for latest dpll init API call]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-06-06 20:33:39 +03:00
Peter Ujfalusi 81c7e03acb CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck
In order to get correct clock dividers for AESS/ABE we need to set the
dpll_abe_m2x2_ck rate to be double of dpll_abe_ck.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-06-06 20:33:34 +03:00