Commit Graph

10 Commits

Author SHA1 Message Date
Timur Tabi 3900fad3d3 powerpc/85xx: re-enable ePAPR byte channel driver in corenet32_smp_defconfig
Commit 7c4b2f09 (powerpc: Update mpc85xx/corenet 32-bit defconfigs)
accidentally disabled the ePAPR byte channel driver in the defconfig for
Freescale CoreNet platforms.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-04 15:33:58 -06:00
Kumar Gala 389a6c527e powerpc/fsl: Update defconfigs to enable some standard FSL HW features
corenet64_smp_defconfig:
 - enabled rapidio

corenet32_smp_defconfig:
 - enabled hugetlbfs, rapidio

mpc85xx_smp_defconfig:
 - enabled P1010RDB, hugetlbfs, SPI, SDHC, Crypto/CAAM

mpc85xx_smp_defconfig:
 - enabled hugetlbfs, SPI, SDHC, Crypto/CAAM

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-04 15:33:58 -06:00
Becky Bruce 41caebd123 powerpc: Enable Hugetlb by default for 32-bit 85xx/corenet
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-07 16:26:23 +11:00
Shengzhou Liu 96cc017c5b powerpc/p3060qds: Add support for P3060QDS board
The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC.
The P3060 Processor combines six e500mc Power Architecture processor cores with
high-performance datapath acceleration architecture(DPAA), CoreNet fabric
infrastructure, as well as network and peripheral interfaces.

P3060QDS Board Overview:
Memory subsystem:
  - 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
  - 128M Bytes NOR flash single-chip memory
  - 16M Bytes SPI flash
  - 8K Bytes AT24C64 I2C EEPROM
Ethernet:
  - 4x1G + 4x1G/2.5G Ethernet controllers
  - 2xRGMII + 1xMII, three VSC8641 PHYs on board
  - Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3
PCIe: Two PCI Express 2.0 controllers/ports
USB:  Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board
I2C:  Four I2C controllers
UART: Supports up to four UARTs
RapidIO: Supports two serial RapidIO ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-03 13:20:47 -05:00
Becky Bruce 7c4b2f099f powerpc: Update mpc85xx/corenet 32-bit defconfigs
Results from updates via make savedefconfig.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-11 23:28:38 -05:00
Mingkai Hu d31337657b powerpc/85xx: Rename p2040_rdb.c to p2041_rdb.c
There's only p2041rdb board for official release, but the p2041 silicon
on the board can be converted to p2040 silicon without XAUI and L2 cache
function, then the board becomes p2040rdb board. so we use the file name
p2041_rdb.c to handle P2040RDB board and P2041RDB board which is also
consistent with the board name under U-Boot.

During the rename we make few other minor changes to the device tree:
* Move USB phy setting into p2041si.dtsi as its SoC not board defined
* Convert PCI clock-frequency to decimal to be more readable

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-06 23:32:57 -05:00
Kim Phillips e09e2fb513 powerpc/85xx: enable caam crypto driver by default
corenet based SoCs have SEC4 h/w, so enable the SEC4 driver,
caam, and the algorithms it supports, and disable the
SEC2/3 driver, talitos.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-08-30 21:27:30 -05:00
Mingkai Hu 3fce1c0ba2 powerpc/85xx: Add p2040 RDB board support
P2040RDB Specification:
-----------------------
2Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
128 Mbyte NOR flash single-chip memory
256 Kbit M24256 I2C EEPROM
16 Mbyte SPI memory
SD connector to interface with the SD memory card
dTSEC1: connected to the Vitesse SGMII PHY (VSC8221)
dTSEC2: connected to the Vitesse SGMII PHY (VSC8221)
dTSEC3: connected to the Vitesse SGMII PHY (VSC8221)
dTSEC4: connected to the Vitesse RGMII PHY (VSC8641)
dTSEC5: connected to the Vitesse RGMII PHY (VSC8641)
I2C1: Real time clock, Temperature sensor
I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM
SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors
UART: supports two UARTs up to 115200 bps for console
USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces
PCIe:
 - Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1
 - Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-08 00:21:32 -05:00
Timur Tabi 59f8df290a powerpc/85xx: add hypervisor config entries to corenet_smp_defconfig
CONFIG_PPC_EPAPR_HV_BYTECHAN adds support for the Freescale hypervisor
byte channel tty driver.

CONFIG_VIRT_DRIVERS and CONFIG_FSL_HV_MANAGER add support for the Freescale
hypervisor management driver.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-08 00:21:31 -05:00
Kumar Gala e6bdc3744e powerpc: Add a defconfig for 'corenet' 32-bit platforms
The e500mc and e5500 based cores are only available on corenet based
SoCs.  We use this name for the P204x, P3040, P4040, P4080, P50x0 SoCs
and any future processors in these families.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-06-22 21:44:50 -05:00