now that we have no users of dev_dbg() in dwc3,
we can safely remove CONFIG_USB_DWC3_DEBUG.
If dev_dbg() is ever strictly necessary - and I
don't see why it would, considering we want to
rely on tracepoints for debug - we will depend
on DYNAMIC_PRINTK to enable such messages.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Registers DWC3's ULPI interface with the ULPI bus when it's
available.
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: David Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This patch adds the ST glue logic to manage the DWC3 HC
on STiH407 SoC family. It manages the powerdown signal,
and configures the internal glue logic and syscfg registers.
[ balbi@ti.com : actually switch over to of_platform_depopulate() ]
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Felipe Balbi <balbi@ti.com>
When we're debugging hard-to-reproduce and time-sensitive
use cases, printk() poses too much overhead. That's when
the kernel's tracing infrastructure comes into play.
This patch implements a few initial tracepoints for the
dwc3 driver. More traces can be added as necessary in order
to ease the task of debugging dwc3.
Reviewed-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Glue layers are starting to have separate
requirements. For example, OMAP's glue layer
is starting to use extcon framework which
no one else needs.
In order to make it clear the proper dependencies,
we are now allowing glue layers to be selectable
so that each glue layer can list their own dependencies
without messing with the core IP driver.
Signed-off-by: Felipe Balbi <balbi@ti.com>
DWC3 controller curretly depends on USB && USB_GADGET.
Some hardware may like to use only host feature on dwc3,
or only gadget feature.
So, removing this dependency of USB_DWC3 on USB and USB_GADGET.
Adding the mode of operaiton of DWC3 also here
HOST/GADGET/DUAL_ROLE based on which features are enabled.
[ balbi@ti.com :
. make sure we have default modes for all possible Kernel
configurations.
. Remove the config -> menuconfig change as it's unnecessary
. switch over to IS_ENABLED() ]
CC: Doug Anderson <dianders@chromium.org>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
commit 93abe8e (clk: add non CONFIG_HAVE_CLK routines)
added clk API stubs when !defined(CONFIG_HAVE_CLK).
This allows us to remove the HAVE_CLK dependency from
Exynos' glue layer and let it compile always.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Adds Exynos Specific Glue layer to support USB peripherals
on Samsung Exynos5 chips.
[ balbi@ti.com : prevent compilation of Exynos glue layer
on platforms which don't provide clk API implementation ]
Signed-off-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
The Designware USB3 IP can be configured with
an internal xHCI. If we're running on such a
version, let's start the xHCI stack.
Signed-off-by: Felipe Balbi <balbi@ti.com>
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Felipe Balbi