Commit Graph

186 Commits

Author SHA1 Message Date
Hans de Goede 1b422ecd27 irqchip: sun7i/sun6i: Disable NMI before registering the handler
It is advisable to disable the NMI before registering the IRQ handler as
registering the IRQ handler unmasks the IRQ on the GIC, so if U-Boot has
left the NMI enabled and the NMI pin is active we will immediately get
an interrupt before any driver has claimed the downstream interrupt of
the NMI.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Carlo Caione <carlo@caione.org>
Cc: maxime.ripard@free-electrons.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1395939759-11135-3-git-send-email-carlo@caione.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-31 11:12:57 +02:00
Carlo Caione 6058bb3628 ARM: sun7i/sun6i: irqchip: Add irqchip driver for NMI controller
Allwinner A20/A31 SoCs have special registers to control / (un)mask /
acknowledge NMI. This NMI controller is separated and independent from GIC.
This patch adds a new irqchip to manage NMI.

Signed-off-by: Carlo Caione <carlo@caione.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Cc: mark.rutland@arm.com
Cc: hdegoede@redhat.com
Link: http://lkml.kernel.org/r/1395256879-8475-2-git-send-email-carlo@caione.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-26 01:00:50 +01:00
Hans de Goede cc3b68fea2 irqchip: sun4i: Simplify sun4i_irq_ack
Now that we only ack irq 0 the code can be simplified a lot.

Also switch from read / modify / write to a simple write clear:
1) This is what the android code does (it has a hack for acking irq 0
   in its unmask code doing this)

2) read / modify / write simply does not make sense for an irq status
   register like this, if the other bits are writeable (and the data sheet says
   they are not) they should be write 1 to clear, since otherwise a read /
   modify / write can race with a device raising an interrupt and then clear
   the pending bit unintentionally

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1394895894-8891-3-git-send-email-hdegoede@redhat.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-19 12:34:29 +01:00
Hans de Goede 915b78ce8e irqchip: sun4i: Use handle_fasteoi_irq for all interrupts
Since the sun4i irq chip does not require any action and clears the interrupt
when the level goes back to inactive, we don't need to mask / unmask for
non oneshot IRQs, to achieve this we make sun4i_irq_ack a nop for all irqs
except irq 0 and use handle_fasteoi_irq for all interrupts.

Now there might be a case when the device reactivates the interrupt
before the RETI. But that does not matter as we run the primary
interrupt handlers with interrupts disabled.

This also allows us to get rid of needing to use 2 irq_chip structs, this
means that the IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED will now influence
all interrupts rather then just irq 0, but that does not matter as the eoi
is now a nop anyways for all interrupts but irq 0.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1394895894-8891-2-git-send-email-hdegoede@redhat.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-19 12:34:29 +01:00
Hans de Goede e9df9e2216 irqchip: sun4i: Don't ack IRQs > 0, fix acking of IRQ 0
All IRQs except for IRQ 0 seem to not need acking, so drop acking for them.

The ENMI needs to have the ack done *after* clearing the interrupt source,
otherwise we will get a spurious interrupt for each real interrupt.

So use the new IRQCHIP_EOI_THREADED flag for this in combination with
handle_fasteoi_irq. This uses a separate irq_chip struct for IRQ 0,
since we only want this behavior for IRQ 0.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: http://lkml.kernel.org/r/1394733834-26839-5-git-send-email-hdegoede@redhat.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-14 13:43:33 +01:00
Hans de Goede 649ff46e5e irqchip: sun4i: Fix a comment about mask register initialization
The comment was claiming that we were masking all irqs, while the code actually
*un*masks all of them.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1394733834-26839-4-git-send-email-hdegoede@redhat.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-14 13:43:33 +01:00
Hans de Goede 56af0416b0 irqchip: sun4i: Fix irq 0 not working
SUN4I_IRQ_VECTOR_REG containing 0 can mean one of 3 things:

1) no more irqs pending
2) irq 0 pending
3) spurious irq

So if we immediately get a reading of 0, check the irq-pending reg
to differentiate between 2 and 3. We only do this once to avoid
the extra check in the common case of 1) hapening after having
read the vector-reg once.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1394733834-26839-3-git-send-email-hdegoede@redhat.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-14 13:43:33 +01:00
Maxime Ripard a7e8b4b519 irqchip: sunxi: Change compatibles
The Allwinner A10 compatibles were following a slightly different compatible
patterns than the rest of the SoCs for historical reasons. Change the compatibles
to match the other pattern in the irq controller driver for consistency.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-14 13:43:32 +01:00
Thomas Gleixner ffb12cf002 Merge branch 'irq/for-gpio' into irq/core
Merge the request/release callbacks which are in a separate branch for
consumption by the gpio folks.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-12 16:01:07 +01:00
Stephen Boyd 1a75b8e645 irqchip: Remove unused include
The "irqchip.h" include here is not needed as the only thing in
irqchip.h is IRQCHIP_DECLARE which this file doesn't use. Drop
it.

Reported-by: Jiri Kosina <jkosina@suse.cz>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Link: http://lkml.kernel.org/r/531F7765.40207@codeaurora.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-12 13:12:04 +01:00
Stephen Boyd 8783dd3a37 irqchip: Remove asmlinkage from static functions
LTO patches add __visible to the asmlinkage define, causing
compilation warnings like:

  drivers/irqchip/irq-gic.c:283:1: warning: 'externally_visible'
  attribute have effect only on public objects [-Wattributes]

Drop asmlinkage here to avoid such warnings.

Reported-by: Olof's autobuilder <build@lixom.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: khilman@linaro.org
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Josh Cartwright <joshc@codeaurora.org>
Cc: Andi Kleen <ak@linux.intel.com>
Link: http://lkml.kernel.org/r/1393980030-17770-1-git-send-email-sboyd@codeaurora.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-12 13:00:41 +01:00
Stephen Boyd 6859358e4b irqchip: gic: Silence sparse warnings
drivers/irqchip/irq-gic.c:53:23: warning: duplicate [noderef]
drivers/irqchip/irq-gic.c:651:6: warning: symbol 'gic_raise_softirq' was not declared. Should it be static?
drivers/irqchip/irq-gic.c:872:29: warning: symbol 'gic_irq_domain_ops' was not declared. Should it be static?
drivers/irqchip/irq-gic.c:977:12: warning: symbol 'gic_of_init' was not declared. Should it be static?

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1393981321-25721-1-git-send-email-sboyd@codeaurora.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-06 11:40:47 +01:00
Stephen Boyd 559ba4b153 irqchip: Silence sparse warning
drivers/irqchip/irqchip.c:27:13: warning: symbol 'irqchip_init'
was not declared. Should it be static?

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: trivial@kernel.org
Link: http://lkml.kernel.org/r/1393981281-25553-1-git-send-email-sboyd@codeaurora.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-06 11:40:47 +01:00
Thomas Gleixner 5c331c8626 irqchip: xtensa: Select only an online cpu
The user space interface does not filter out offline cpus. It merily
verifies that the mask contains at least one online cpu. So the
selector in the irq chip implementation needs to make sure to pick
only an online cpu because otherwise:

     Offline Core 1
     Set affinity to 0xe
     Selector will pick first set bit, i.e. core 1

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Chris Zankel <chris@zankel.net>
Cc: xtensa <linux-xtensa@linux-xtensa.org>
2014-03-04 17:37:55 +01:00
Jason Cooper eb9cf4e8ec Revert irqchip: irq-dove: Add PMU interrupt controller
This reverts commit 40b367d95f.

Russell King has raised the idea of creating a proper PMU driver for
this SoC that would incorporate the functionality currently in this
driver. It would also cover the use case for the graphics subsystem on
this SoC.

To prevent having to maintain the devicetree ABI for this limited
interrupt-handler driver, we revert the driver before it hits a mainline
tagged release (eg v3.15).

Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@googlemail.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Link: http://lkml.kernel.org/r/1393911160-7688-1-git-send-email-jason@lakedaemon.net
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-04 11:10:17 +01:00
James Hogan f229006ec6 irq-metag*: stop set_affinity vectoring to offline cpus
Fix irq_set_affinity callbacks in the Meta IRQ chip drivers to AND
cpu_online_mask into the cpumask when picking a CPU to vector the
interrupt to.

As Thomas pointed out, the /proc/irq/$N/smp_affinity interface doesn't
filter out offline CPUs, so without this patch if you offline CPU0 and
set an IRQ affinity to 0x3 it vectors the interrupt onto CPU0 even
though it is offline.

Reported-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-metag@vger.kernel.org
Cc: stable@vger.kernel.org
2014-02-25 22:35:06 +00:00
Thomas Gleixner d0e3a9719f irqchip mvebu changes for v3.15
- armada-370-xp
     - add MSI helper
     - MPIC chained handler
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Merge tag 'irqchip-mvebu-3.15' of git://git.infradead.org/linux-mvebu into irq/core

irqchip mvebu changes for v3.15

 - armada-370-xp
    - add MSI helper
    - MPIC chained handler

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-02-22 10:57:06 +01:00
Ezequiel Garcia bc69b8adfe irqchip: armada-370-xp: Setup a chained handler for the MPIC
The new Armada 375 and Armada 38x Marvell SoCs are based on Cortex-A9
CPU cores and use the ARM GIC as their main interrupt controller.
However, for various purposes (wake-up from suspend, MSI interrupts),
they have kept a separate MPIC interrupt controller, acting as a slave
to the GIC. This MPIC was already used as the primary controller on
previous Marvell SoCs, so this commit extends the existing driver to
allow the MPIC to be used as a GIC slave.

Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-22 06:12:29 +00:00
Ezequiel Garcia 9b8cf779f9 irqchip: armada-370-xp: Add helper for the MSI IRQ handling
Introduce a helper function to handle the MSI interrupts. This makes
the code more readable. In addition, this will allow to introduce a
chained IRQ handler mechanism, which is needed in situations where the
MPIC is used as a slave to another interrupt controller.

Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-22 06:12:13 +00:00
Jason Cooper 3efca1d156 mvebu irqchip fixes for v3.13
- armada-370-xp
     - fix races is MSI and IPI
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Merge tag 'tags/mvebu-irqchip-fixes-3.13' into mvebu/irqchip

mvebu irqchip fixes for v3.13

 - armada-370-xp
    - fix races is MSI and IPI
2014-02-22 06:11:45 +00:00
Thomas Gleixner ec79b577f0 irqchip mvebu fixes for v3.14
- orion:
     - fixes for clearing bridge cause register, and clearing stale interrupts
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Merge tag 'irqchip-mvebu-fixes-3.14' of git://git.infradead.org/linux-mvebu into irq/urgent

irqchip mvebu fixes for v3.14

 - orion:
    - fixes for clearing bridge cause register, and clearing stale interrupts

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-02-21 23:57:33 +01:00
Andrew Lunn d86e9af633 irqchip: orion: Fix getting generic chip pointer.
Enabling SPARSE_IRQ shows up a bug in the irq-orion bridge interrupt
handler. The bridge interrupt is implemented using a single generic
chip. Thus the parameter passed to irq_get_domain_generic_chip()
should always be zero.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Fixes: 9dbd90f17e ("irqchip: Add support for Marvell Orion SoCs")
Cc: <stable@vger.kernel.org> # v3.11+
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-21 21:46:56 +00:00
Thomas Gleixner ddf2965d77 mvebu irqchip changes for v3.14
- add Dove PMU interrupt controller
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Merge tag 'mvebu-irqchip-3.14' of git://git.infradead.org/linux-mvebu into irq/core

mvebu irqchip changes for v3.14

 - add Dove PMU interrupt controller

Duh. I completely forgot about that one...

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-02-18 21:27:56 +01:00
Sebastian Hesselbarth e0318ec3bf irqchip: orion: clear stale interrupts in irq_startup
Bridge IRQ_CAUSE bits are asserted regardless of the corresponding bit in
IRQ_MASK register. To avoid interrupt events on stale irqs, we have to clear
them before unmask. This installs an .irq_startup callback to ensure stale
irqs are cleared before initial unmask.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: <stable@vger.kernel.org>: f56c0738b5c2: "irqchip: orion: clear bridge cause register on init"
Cc: <stable@vger.kernel.org>: 38bd80b84fca: "irqchip: orion: use handle_edge_irq on bridge irqs"
Cc: <stable@vger.kernel.org> # v3.10+
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-06 18:03:32 +00:00
Sebastian Hesselbarth 5f40067fc8 irqchip: orion: use handle_edge_irq on bridge irqs
Bridge irqs are edge-triggered, i.e. they get asserted on low-to-high
transitions and not on the level of the downstream interrupt line.
This replaces handle_level_irq by the more appropriate handle_edge_irq.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: <stable@vger.kernel.org>: f56c0738b5c2: "irqchip: orion: clear bridge cause register on init"
Cc: <stable@vger.kernel.org> # v3.10+
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-06 18:03:22 +00:00
Sebastian Hesselbarth 7b119fd1bd irqchip: orion: clear bridge cause register on init
It is good practice to mask and clear pending irqs on init. We already
mask all irqs, so also clear the bridge irq cause register.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.10+
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-06 18:03:08 +00:00
Linus Torvalds ef42c58a5b Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
 "This lot provides:

   * Bugfixes for armada irq controller
   * Updates to renesas irq chip
   * Support for the TI-NSPIRE irq controller

  Not strictly a bug fix only pull request, but important updates for
  some of the arm Socs which I completely forgot to send last week.

  Seems like my obliviousness is getting worse, I just can't remember
  when it started"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip: Add support for TI-NSPIRE irqchip
  irqchip: renesas-irqc: Enable mask on suspend
  irqchip: renesas-irqc: Use lazy disable
  irqchip: armada-370-xp: fix MSI race condition
  irqchip: armada-370-xp: fix IPI race condition
2014-02-05 16:02:53 -08:00
Olof Johansson 167eeb4700 mvebu fixes for v3.13 (incremental #2)
- allow building and booting DT and non-DT plat-orion SoCs
  - catch proper return value for kirkwood_pm_init()
  - properly check return of of_iomap to solve boot hangs (mirabox, others)
  - remove a compile warning on Armada 370 with non-SMP.
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Merge tag 'mvebu-fixes-3.13-2' of git://git.infradead.org/linux-mvebu into fixes

mvebu fixes for v3.13 (incremental #2)

 - allow building and booting DT and non-DT plat-orion SoCs
 - catch proper return value for kirkwood_pm_init()
 - properly check return of of_iomap to solve boot hangs (mirabox, others)
 - remove a compile warning on Armada 370 with non-SMP.

* tag 'mvebu-fixes-3.13-2' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: fix compilation warning on Armada 370 (i.e. non-SMP)
  ARM: mvebu: Fix kernel hang in mvebu_soc_id_init() when of_iomap failed
  ARM: kirkwood: kirkwood_pm_init() should return void
  ARM: orion: provide C-style interrupt handler for MULTI_IRQ_HANDLER

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-01-31 14:59:28 -08:00
Linus Torvalds 9b83d851a2 Xtensa patchset for 3.14-rc1
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Merge tag 'xtensa-next-20140123' of git://github.com/czankel/xtensa-linux

Pull Xtensa patches from Chris Zankel:
 "The major changes are adding support for SMP for Xtensa, fixing and
  cleaning up the ISS (simulator) network driver, and better support for
  device trees"

* tag 'xtensa-next-20140123' of git://github.com/czankel/xtensa-linux: (40 commits)
  xtensa: implement ndelay
  xtensa: clean up udelay
  xtensa: enable HAVE_PERF_EVENTS
  xtensa: remap io area defined in device tree
  xtensa: support default device tree buses
  xtensa: initialize device tree clock sources
  xtensa: xtfpga: fix definitions of platform devices
  xtensa: standardize devicetree cpu compatible strings
  xtensa: avoid duplicate of IO range definitions
  xtensa: fix ATOMCTL register documentation
  xtensa: Enable irqs after cpu is set online
  xtensa: ISS: raise network polling rate to 10 times/sec
  xtensa: remove unused XTENSA_ISS_NETWORK Kconfig parameter
  xtensa: ISS: avoid simple_strtoul usage
  xtensa: Switch to sched_clock_register()
  xtensa: implement CPU hotplug
  xtensa: add SMP support
  xtensa: add MX irqchip
  xtensa: clear timer IRQ unconditionally in its handler
  xtensa: clean up do_interrupt/do_IRQ
  ...
2014-01-25 10:49:30 -08:00
Linus Torvalds 0ba3307a8e ARM: driver updates for 3.14
Updates of SoC-near drivers and other driver updates that makes more sense to
 take through our tree.
 
 The largest part of this is a conversion of device registration for some
 renesas shmobile/sh devices over to use resources. This has required
 coordination with the corresponding arch/sh changes, and we've agreed
 to merge the arch/sh changes through our tree.
 
 Added in this branch is support for Trusted Foundations secure firmware,
 which is what is used on many of the commercial Nvidia Tegra products
 that are in the market, including the Nvidia Shield. The code is local
 to arch/arm at this time since it's uncertain whether it will be shared
 with arm64 longer-term, if needed we will refactor later.
 
 A couple of new RTC drivers used on ARM boards, merged through our tree
 on request by the RTC maintainer.
 
 ... plus a bunch of smaller updates across the board, gpio conversions
 for davinci, etc.
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Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM driver updates from Olof Johansson:
 "Updates of SoC-near drivers and other driver updates that makes more
  sense to take through our tree.

  The largest part of this is a conversion of device registration for
  some renesas shmobile/sh devices over to use resources.  This has
  required coordination with the corresponding arch/sh changes, and
  we've agreed to merge the arch/sh changes through our tree.

  Added in this branch is support for Trusted Foundations secure
  firmware, which is what is used on many of the commercial Nvidia Tegra
  products that are in the market, including the Nvidia Shield.  The
  code is local to arch/arm at this time since it's uncertain whether it
  will be shared with arm64 longer-term, if needed we will refactor
  later.

  A couple of new RTC drivers used on ARM boards, merged through our
  tree on request by the RTC maintainer.

  ... plus a bunch of smaller updates across the board, gpio conversions
  for davinci, etc"

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (45 commits)
  watchdog: davinci: rename platform driver to davinci-wdt
  tty: serial: Limit msm_serial_hs driver to platforms that use it
  mmc: msm_sdcc: Limit driver to platforms that use it
  usb: phy: msm: Move mach dependent code to platform data
  clk: versatile: fixup IM-PD1 clock implementation
  clk: versatile: pass a name to ICST clock provider
  ARM: integrator: pass parent IRQ to the SIC
  irqchip: versatile FPGA: support cascaded interrupts from DT
  gpio: davinci: don't create irq_domain in case of unbanked irqs
  gpio: davinci: use chained_irq_enter/chained_irq_exit API
  gpio: davinci: add OF support
  gpio: davinci: remove unused variable intc_irq_num
  gpio: davinci: convert to use irqdomain support.
  gpio: introduce GPIO_DAVINCI kconfig option
  gpio: davinci: get rid of DAVINCI_N_GPIO
  gpio: davinci: use {readl|writel}_relaxed() instead of __raw_*
  serial: sh-sci: Add OF support
  serial: sh-sci: Add device tree bindings documentation
  serial: sh-sci: Remove platform data mapbase and irqs fields
  serial: sh-sci: Remove platform data scbrr_algo_id field
  ...
2014-01-23 18:49:36 -08:00
Linus Torvalds dfd10e7ae6 ARM: SoC platform changes for 3.14
New core SoC-specific changes.
 
 New platforms:
 * Introduction of a vendor, Hisilicon, and one of their SoCs with some
   random numerical product name.
 * Introduction of EFM32, embedded platform from Silicon Labs (ARMv7m, i.e. !MMU).
 * Marvell Berlin series of SoCs, which include the one in Chromecast.
 * MOXA platform support, ARM9-based platform used mostly in industrial products
 * Support for Freescale's i.MX50 SoC.
 
 Other work:
 * Renesas work for new platforms and drivers, and conversion over to
   more multiplatform-friendly device registration schemes.
 * SMP support for Allwinner sunxi platforms.
 * ... plus a bunch of other stuff across various platforms.
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Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "New core SoC-specific changes.

  New platforms:
   * Introduction of a vendor, Hisilicon, and one of their SoCs with
     some random numerical product name.
   * Introduction of EFM32, embedded platform from Silicon Labs (ARMv7m,
     i.e. !MMU).
   * Marvell Berlin series of SoCs, which include the one in Chromecast.
   * MOXA platform support, ARM9-based platform used mostly in
     industrial products
   * Support for Freescale's i.MX50 SoC.

  Other work:
   * Renesas work for new platforms and drivers, and conversion over to
     more multiplatform-friendly device registration schemes.
   * SMP support for Allwinner sunxi platforms.
   * ... plus a bunch of other stuff across various platforms"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (201 commits)
  ARM: tegra: fix tegra_powergate_sequence_power_up() inline
  ARM: msm_defconfig: Update for multi-platform
  ARM: msm: Move MSM's DT based hardware to multi-platform support
  ARM: msm: Only build timer.c if required
  ARM: msm: Only build clock.c on proc_comm based platforms
  ARM: ux500: Enable system suspend with WFI support
  ARM: ux500: turn on PRINTK_TIME in u8500_defconfig
  ARM: shmobile: r8a7790: Fix I2C controller names
  ARM: msm: Simplify ARCH_MSM_DT config
  ARM: msm: Add support for MSM8974 SoC
  ARM: sunxi: select ARM_PSCI
  MAINTAINERS: Update Allwinner sunXi maintainer files
  ARM: sunxi: Select RESET_CONTROLLER
  ARM: imx: improve the comment of CCM lpm SW workaround
  ARM: imx: improve status check of clock gate
  ARM: imx: add necessary interface for pfd
  ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100
  ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support
  ARM: imx: Add cpu frequency scaling support
  ARM i.MX35: Add devicetree support.
  ...
2014-01-23 18:40:49 -08:00
Thomas Gleixner b6628210ac mvebu irqchip fixes for v3.13
- armada-370-xp
     - fix races is MSI and IPI
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Merge tag 'mvebu-irqchip-fixes-3.13' of git://git.infradead.org/linux-mvebu into irq/core

mvebu irqchip fixes for v3.13

 - armada-370-xp
    - fix races is MSI and IPI
2014-01-22 21:56:04 +01:00
Daniel Tang 397e7b5157 irqchip: Add support for TI-NSPIRE irqchip
This patch adds support for the interrupt controllers found in some
TI-Nspire models.

FIQ support was taken out to simplify the driver code and may be added
in later. Since Linux on this platform doesn't really use FIQs, this
wasn't really that important in the first place.

[ tglx: Made zevio_handle_irq static and reordered __init functions ]

Signed-off-by: Daniel Tang <dt.tangr@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Link: http://lkml.kernel.org/r/1386223937-12189-1-git-send-email-dt.tangr@gmail.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-01-22 21:48:55 +01:00
Magnus Damm 43881ec7a8 irqchip: renesas-irqc: Enable mask on suspend
Now when lazy interrupt disable has been enabled in the driver
then extend the code to set IRQCHIP_MASK_ON_SUSPEND which tells
the core that only IRQs marked as wakeups need to stay enabled
during Suspend-to-RAM.

Signed-off-by: Magnus Damm <damm@opensource.se>
Cc: rob.herring@calxeda.com
Cc: grant.likely@secretlab.ca
Cc: horms@verge.net.au
Link: http://lkml.kernel.org/r/20131204120556.29642.27021.sendpatchset@w520
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-01-22 21:48:55 +01:00
Magnus Damm 3aba556053 irqchip: renesas-irqc: Use lazy disable
Set the ->irq_enable() and ->irq_disable() methods to NULL
to enable lazy disable of interrupts. This by itself provides
some level of optimization, but is mainly enabled as ground
work for future Suspend-to-RAM wake up support.

Signed-off-by: Magnus Damm <damm@opensource.se>
Cc: rob.herring@calxeda.com
Cc: grant.likely@secretlab.ca
Cc: horms@verge.net.au
Link: http://lkml.kernel.org/r/20131204120546.29642.15772.sendpatchset@w520
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-01-22 21:48:55 +01:00
Arnaud Ebalard 19e61d4140 ARM: mvebu: fix compilation warning on Armada 370 (i.e. non-SMP)
The following appears during compilation for an Armada 370 target
because 'irq_controller_lock' is used only when CONFIG_SMP is
enabled:

 drivers/irqchip/irq-armada-370-xp.c:62:8: warning: 'irq_controller_lock' defined but not used [-Wunused-variable]

Fix that warning by moving declaration of 'irq_controller_lock'
inside existing #ifdef.

Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-01-21 00:55:47 +00:00
Kevin Hilman 099c2e9ef6 Some non-urgent fixes to enable am335x features, update documentation,
and to remove unnecessary double initialization for the GPMC code.
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Merge tag 'omap-for-v3.14/fixes-not-urgent-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical

From Tony Lindgren:
Some non-urgent fixes to enable am335x features, update documentation,
and to remove unnecessary double initialization for the GPMC code.

* tag 'omap-for-v3.14/fixes-not-urgent-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (238 commits)
  ARM: OMAP2+: gpmc: Move legacy GPMC width setting
  ARM: OMAP2+: gpmc: Introduce gpmc_set_legacy()
  ARM: OMAP2+: gpmc: Move initialization outside the gpmc_t condition
  ARM: OMAP2+: board-generic: update SoC compatibility strings
  Documentation: dt: OMAP: explicitly state SoC compatible strings
  ARM: OMAP2+: enable AM33xx SOC EVM audio
  ARM: OMAP2+: Select USB PHY for AM335x SoC
  +Linux 3.13-rc5
2014-01-14 14:20:19 -08:00
Max Filippov 26a8e96a8b xtensa: add MX irqchip
MX is an interrupt distributor used in some SMP-capable xtensa
configurations.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2014-01-14 10:19:58 -08:00
Max Filippov cbd1de2e8e xtensa: move built-in PIC to drivers/irqchip
Extract xtensa built-in interrupt controller implementation from
xtensa/kernel/irq.c and move it to other irqchips, providing way to
instantiate it from the device tree.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2014-01-14 10:19:56 -08:00
Barry Song a87010ef32 irqchip: sirf: set IRQ_LEVEL status_flags
SiRF internal interrupts are using level trigger. we need to tell the irq
core this information. otherwise, we might get some problems as below
1. disable_irq(n)
here irq core will mark the disabled flag but still keep the irq enabled
due to involved lazy-disable
2. doing someting after disable_irq(n)
in step 2, if one interrupt n comes, irq core will mark it as pending and
mask the HW interrupt really. we name the coming interrupt as "X".
3. enable_irq(n)
this will unmask the interrupt, so the level-trigger HW interrupt will come
again, irq_handler will enter as "E1". after that, irq core will also check
whether irq n is pending, if yes, and pending interrupt is not level-trigger,
irq core will execute the pending irq_handler.
so if we don't set the IRQ_LEVEL flag here, irq core will execute pending
X again as "E2", but actually the pending interrupt has been handled by "E1".
that makes a level-trigger HW interrupt is executed twice.

here we fix the issue to avoid redundant interrupt overload.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Huayi Li <Huayi.Li@csr.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2014-01-08 22:02:14 -08:00
Olof Johansson 3d7e0207ce Some Integrator patches that matured for v3.14:
- Use PATCH_PHYS_TO_VIRT and AUTO_ZRELADDR.
 
 - Support cascaded interrupts on the SIC.
 
 - Complete clock implementation for the IM-PD1.
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Merge tag 'integrator-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/drivers

From Linus Walleij:
Some Integrator patches that matured for v3.14:

- Use PATCH_PHYS_TO_VIRT and AUTO_ZRELADDR.
- Support cascaded interrupts on the SIC.
- Complete clock implementation for the IM-PD1.

* tag 'integrator-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
  clk: versatile: fixup IM-PD1 clock implementation
  clk: versatile: pass a name to ICST clock provider
  ARM: integrator: pass parent IRQ to the SIC
  irqchip: versatile FPGA: support cascaded interrupts from DT
  ARM: integrator: Default enable ARM_PATCH_PHYS_VIRT, AUTO_ZRELADDR

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-01-03 21:55:29 -08:00
Linus Walleij bdd272cbb9 irqchip: versatile FPGA: support cascaded interrupts from DT
The Versatile FPGA interrupt controller supports cascading interrupts,
i.e. that its output is connected to the input of another interrupt
controller. This makes it possible to pass a parent interrupt from
the device tree and print it in the boot log if applicable.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-03 22:26:13 +01:00
Olof Johansson a7dedb4fea DaVinci GPIO driver updates
---------------------------
 
 This pull request contains updates
 to DaVinci GPIO driver and the
 resultant platform code changes. The
 updates include DT-conversion and
 changes to make the driver cross-platform
 ready.
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Merge tag 'davinci-for-v3.14/gpio' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers

From Sekhar Nori:
DaVinci GPIO driver updates
---------------------------

This pull request contains updates to DaVinci GPIO driver and the
resultant platform code changes. The updates include DT-conversion and
changes to make the driver cross-platform ready.

* tag 'davinci-for-v3.14/gpio' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  gpio: davinci: don't create irq_domain in case of unbanked irqs
  gpio: davinci: use chained_irq_enter/chained_irq_exit API
  gpio: davinci: add OF support
  gpio: davinci: remove unused variable intc_irq_num
  gpio: davinci: convert to use irqdomain support.
  gpio: introduce GPIO_DAVINCI kconfig option
  gpio: davinci: get rid of DAVINCI_N_GPIO
  gpio: davinci: use {readl|writel}_relaxed() instead of __raw_*

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-01-02 11:45:27 -08:00
Olof Johansson 9d6b65e945 Renesas ARM based SoC IRQC Driver Updates for v3.14
* Simplify irq_set_type() method
 * Enable mask on suspend
 * Use lazy disable
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Merge tag 'renesas-irqc-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers

From Simon Horman:
Renesas ARM based SoC IRQC Driver Updates for v3.14

* Simplify irq_set_type() method
* Enable mask on suspend
* Use lazy disable

* tag 'renesas-irqc-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  irq-renesas-irqc: simplify irq_set_type() method
  irqchip: renesas-irqc: Enable mask on suspend
  irqchip: renesas-irqc: Use lazy disable

Signed-off-by: Olof Johansson <olof@lixom.net>
2013-12-29 13:26:13 -08:00
Sergei Shtylyov ce70af1880 irq-renesas-irqc: simplify irq_set_type() method
Value 0 of the sense  selection field of CONFIG_n register means "disable event
detection" and serves in irqc_sense[] for marking the invalid values of the IRQ
type (by just omitting initializers). There is no need for INTC_IRQ_SENSE_VALID
and hence INTC_IRQ_SENSE() as all field values matching to the  valid IRQ types
are non-zero anyway.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-12-23 09:27:17 +09:00
Kevin Hilman 95fcfa70f3 Renesas ARM based SoC fixes for v3.13
* r8a7790 (R-Car H1) SoC
   - Correct GPIO resources in DT.
 
     This problem has been present since GPIOs were added to the r8a7790 SoC
     by f98e10c88a ("ARM: shmobile: r8a7790: Add GPIO controller
     devices to device tree") in v3.12-rc1.
 
 * irqchip renesas-intc-irqpin
   - Correct register bitfield shift calculation
 
     This bug has been present since the renesas-intc-irqpin driver was
     introduced by 443580486e ("irqchip: Renesas INTC External IRQ pin
     driver") in v3.10-rc1
 
 * Lager board
   - Do not build the phy fixup unless CONFIG_PHYLIB is enabled
 
     This problem was introduced by 48c8b96f21
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Merge tag 'renesas-fixes-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes

From Simon Horman:
Renesas ARM based SoC fixes for v3.13

* r8a7790 (R-Car H1) SoC
  - Correct GPIO resources in DT.

    This problem has been present since GPIOs were added to the r8a7790 SoC
    by f98e10c88a ("ARM: shmobile: r8a7790: Add GPIO controller
    devices to device tree") in v3.12-rc1.

* irqchip renesas-intc-irqpin
  - Correct register bitfield shift calculation

    This bug has been present since the renesas-intc-irqpin driver was
    introduced by 443580486e ("irqchip: Renesas INTC External IRQ pin
    driver") in v3.10-rc1

* Lager board
  - Do not build the phy fixup unless CONFIG_PHYLIB is enabled

    This problem was introduced by 48c8b96f21

* tag 'renesas-fixes-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: r8a7790: Fix GPIO resources in DTS
  irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation
  ARM: shmobile: lager: phy fixup needs CONFIG_PHYLIB

Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-12-20 11:28:30 -08:00
Kevin Hilman 490b929d42 Merge branch 'efm32/soc' into next/soc
From Uwe Kleine-König:
* efm32/soc: (1003 commits)
  ARM: device trees for Energy Micro's EFM32 Cortex-M3 SoCs
  ARM: new platform for Energy Micro's EFM32 Cortex-M3 SoCs
  +Linux 3.13-rc4

Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-12-20 08:59:30 -08:00
Lior Amsalem c7f7bd4a13 irqchip: armada-370-xp: fix MSI race condition
In the Armada 370/XP driver, when we receive an IRQ 1, we read the
list of doorbells that caused the interrupt from register
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS. This gives the list of MSIs that
were generated. However, instead of acknowledging only the MSIs that
were generated, we acknowledge *all* the MSIs, by writing
~MSI_DOORBELL_MASK in the ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS register.

This creates a race condition: if a new MSI that isn't part of the
ones read into the temporary "msimask" variable is fired before we
acknowledge all MSIs, then we will simply loose it.

It is important to mention that this ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS
register has the following behavior: "A CPU write of 0 clears the bits
in this field. A CPU write of 1 has no effect". This is what allows us
to simply write ~msimask to acknoledge the handled MSIs.

Notice that the same problem is present in the IPI implementation, but
it is fixed as a separate patch, so that this IPI fix can be pushed to
older stable versions as appropriate (all the way to 3.8), while the
MSI code only appeared in 3.13.

Signed-off-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-12-13 16:34:40 +00:00
Lior Amsalem a6f089e95b irqchip: armada-370-xp: fix IPI race condition
In the Armada 370/XP driver, when we receive an IRQ 0, we read the
list of doorbells that caused the interrupt from register
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS. This gives the list of IPIs that
were generated. However, instead of acknowledging only the IPIs that
were generated, we acknowledge *all* the IPIs, by writing
~IPI_DOORBELL_MASK in the ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS register.

This creates a race condition: if a new IPI that isn't part of the
ones read into the temporary "ipimask" variable is fired before we
acknowledge all IPIs, then we will simply loose it. This is causing
scheduling hangs on SMP intensive workloads.

It is important to mention that this ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS
register has the following behavior: "A CPU write of 0 clears the bits
in this field. A CPU write of 1 has no effect". This is what allows us
to simply write ~ipimask to acknoledge the handled IPIs.

Notice that the same problem is present in the MSI implementation, but
it will be fixed as a separate patch, so that this IPI fix can be
pushed to older stable versions as appropriate (all the way to 3.8),
while the MSI code only appeared in 3.13.

Signed-off-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: stable@vger.kernel.org # v3.8+
Fixes: 344e873e56 'arm: mvebu: Add IPI support via doorbells'
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-12-13 16:34:04 +00:00
Sebastian Hesselbarth 350d71b94f irqchip: add DesignWare APB ICTL interrupt controller
This adds an irqchip driver and corresponding devicetree binding for the
secondary interrupt controllers based on Synopsys DesignWare IP dw_apb_ictl.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Jisheng Zhang <jszhang@marvell.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
2013-12-13 16:29:40 +01:00