The PM1B registers are mirrors of the PM1A registers with
different bits actually implemented. From the ACPI specification:
"Although the bits can be split between the two register blocks
(each register block has a unique pointer within the FADT), the bit
positions are maintained. The register block with unimplemented
bits (that is, those implemented in the other register block)
always returns zeros, and writes have no side effects"
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
This function was writing an optional PM1B status register
twice. The existing call to the low-level acpi_hw_register_write
automatically handles a possibly split PM1 A/B register.
ACPICA BZ 751.
http://www.acpica.org/bugzilla/show_bug.cgi?id=751
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
On read, shift B register bits above the A bits. On write,
shift B bits down to zero before writing the B register. New:
acpi_hw_read_multiple, acpi_hw_write_multiple. These two functions now
transparently handle the (possible) split registers for PM1 Status,
Enable, and Control.
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Add new globals for the PM1 status registers (A/B), similar to the
way the PM1 enable registers are handled. Instead of overloading
the FADT Event Register blocks. This makes the code clearer and
less prone to error.
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Bob Moore