3 Commits

Author	SHA1	Message	Date
Jerome Brunet	b68fb7871e	clk: meson: mpll: correct N2 maximum value ... Gxbb datasheet says N2 maximum value is 127 but the register field is 9 bits wide, the maximum value should 511. Test shows value greater than 127, all the way to 511, works well Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-9-jbrunet@baylibre.com	2017-03-27 12:30:38 -07:00
Jerome Brunet	007e6e5c5f	clk: meson: mpll: add rw operation ... This patch adds new callbacks to the meson-mpll driver to control and set the pll rate. For this, we also need to add the enable bit and sdm enable bit. The corresponding parameters are added to mpll data structure. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-6-jbrunet@baylibre.com	2017-03-27 12:30:18 -07:00
Michael Turquette	1c50da4f27	clk: meson: add mpll support ... MPLLs are adjustable rate clocks derived from PLLs. On both Meson8b and GXBB they appear to be only derived from fixed_pll. Add support for these clock types so that they can be added to their respective drivers. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>	2016-06-22 18:02:59 -07:00