Commit Graph

17 Commits

Author SHA1 Message Date
Konrad Dybcio dde6805690 mailbox: qcom: Add msm8994 apcs compatible
MSM8994 has an APCS block similar to 8916, but
with a different clock driver due to the former
one having 2 clusters.

Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-08-03 23:31:34 -05:00
Konrad Dybcio cfbf813e59 mailbox: qcom: Add sdm660 hmss compatible
The Qualcomm SDM660 platform has a APCS HMSS GLOBAL block, add the
compatible for this.

Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-08-03 23:30:09 -05:00
Sivaprakash Murugesan e9f901dc05 mailbox: qcom: Add ipq6018 apcs compatible
The Qualcomm ipq6018 has apcs block, add compatible for the same. Also,
the ipq6018 apcs provides a clock functionality similar to msm8916 but
the clock driver is different.

Create a child device based on the apcs compatible for the clock
controller functionality.

Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-06-10 22:43:57 -05:00
Sivaprakash Murugesan 9b007938ae mailbox: qcom: Add clock driver name in apcs mailbox driver data
Some apcs mailbox devices supports a clock driver, the compatible
strings of devices supporting clock driver along with the clock driver
name are maintained in a separate structure within the mailbox driver.
And the clock driver is added based on device match.

With increase in number of devices supporting the clock feature move the
clock driver name inside the driver data. so that we can use a single
API to get the register offset of mailbox driver and clock driver name
together, and the clock driver will be added based on the driver data.

Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-06-10 22:43:51 -05:00
Jorge Ramirez-Ortiz 556a0964e2 mailbox: qcom-apcs: fix max_register value
The mailbox length is 0x1000 hence the max_register value is 0xFFC.

Fixes: c6a8b171ca ("mailbox: qcom: Convert APCS IPC driver to use
regmap")
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17 00:54:29 -05:00
Gokul Sriram Palanisamy 88ae25e46c mailbox: qcom: Add support for IPQ8074 APCS
Add support of IPQ8074 with IPC register offset as 8.

Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17 00:53:35 -05:00
Sibi Sankar 08a81d3ac8 mailbox: qcom: Add support for Qualcomm SM8150 and SC7180 SoCs
Add the corresponding APSS shared offset for SM8150 and SC7180 SoCs.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17 00:46:24 -05:00
Jorge Ramirez-Ortiz 16d52f336b mbox: qcom: replace integer with valid macro
Use the correct macro when registering the platform device.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17 00:46:05 -05:00
Jorge Ramirez-Ortiz 78c86458a4 mbox: qcom: add APCS child device for QCS404
There is clock controller functionality in the APCS hardware block of
qcs404 devices similar to msm8916.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17 00:46:00 -05:00
Thomas Gleixner 97fb5e8d9b treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 and
  only version 2 as published by the free software foundation this
  program is distributed in the hope that it will be useful but
  without any warranty without even the implied warranty of
  merchantability or fitness for a particular purpose see the gnu
  general public license for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 294 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-05 17:36:37 +02:00
Thierry Reding 83dd44a17d mailbox: qcom-apcs: Use device-managed registration API
Get rid of some boilerplate driver removal code by using the newly added
device-managed registration API.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-12-21 16:49:25 -06:00
Bjorn Andersson 0a01fa940e mailbox: qcom: Add QCS404 APPS Global compatible
Add support for the QCS404 APPS Global block with IPC register at offset
8.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-09-29 12:42:39 +05:30
Sibi Sankar 05e99a7d14 mailbox: Add support for Qualcomm SDM845 SoCs
Add the corresponding APSS shared offset for SDM845 SoC

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-06-06 22:21:59 +05:30
Bjorn Andersson 61a2f6db77 mailbox: qcom: Add msm8998 hmss compatible
The Qualcomm MSM8998 platform has a APCS HMSS GLOBAL block, add the
compatible for this.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-06-06 22:21:59 +05:30
Georgi Djakov c815d769b5 mailbox: qcom: Create APCS child device for clock controller
There is a clock controller functionality provided by the APCS hardware
block of msm8916 devices. The device-tree would represent an APCS node
with both mailbox and clock provider properties.
Create a platform child device for the clock controller functionality so
the driver can probe and use APCS as parent.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-02-04 12:16:23 +05:30
Georgi Djakov c6a8b171ca mailbox: qcom: Convert APCS IPC driver to use regmap
This hardware block provides more functionalities that just IPC. Convert
it to regmap to allow other child platform devices to use the same regmap.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-02-04 12:16:09 +05:30
Bjorn Andersson 25bfee16d5 mailbox: Introduce Qualcomm APCS IPC driver
This implements a driver that exposes the IPC bits found in the APCS
Global block in various Qualcomm platforms. The bits are used to signal
inter-processor communication signals from the application CPU to other
masters.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2017-06-14 17:47:19 +05:30