hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
647,935 Commits 9 Branches 1 Tag 5 GiB
Commit Graph

2 Commits

Author SHA1 Message Date
Scott Telford bebbc4bcf3 xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config. 
Add module parameter xilinx_uartps.rx_trigger_level=32 to command line
options for CSP to set Rx watermark for xuartps driver lower than the
default value, to avoid UART overruns at 115200 bps.

Signed-off-by: Scott Telford <stelford@cadence.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
 2016-09-19 11:51:32 -07:00
Scott Telford 23c2b9321b xtensa: Added Cadence CSP kernel configuration for Xtensa 
Added defconfig, device tree and Xtensa variant header files for the
Cadence Configurable System Platform "xt_lnx" processor configuration.

Signed-off-by: Scott Telford <stelford@cadence.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
 2016-09-09 18:39:09 -07:00