The following patches make use of vendor names:
* ricoh (Ricoh Co. Ltd.);
* qnap (QNAP Systems, Inc.);
* sii (Seiko Instruments, Inc.); and
* synology (Synology, Inc.)
Add them to the vendor prefix list.
Signed-off-by: Ben Peddell <klightspeed@killerwolves.net>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit updates the documentation that describes the various
families of SOCs produced by Marvell, together with the corresponding
available technical documents. It adds Armada 375 and Armada 38x, and
adds a link to the product brief for the already supported Armada 370.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds the basic support for the Armada 380 and Armada 385
SOCs. These SoCs share most of their IP with the Armada 370/XP
SoCs. The main difference is the use of a Cortex A9 CPU instead of the
PJ4B CPU. The Armada 380 is a single core Cortex-A9, while the Armada
385 is a dual-core Cortex-A9.
The support is introduced in board-v7.c, together with Armada 370/XP,
but a separate DT structure is added, because Armada 38x will need a
different set of SMP operations when the SMP support is introduced.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Early versions of Armada 375 SoC have a bug where the BootROM leaves
an external data abort pending. The kernel is hit by this data abort
as soon as it enters userspace, because it unmasks the data aborts at
this moment. We register a custom abort handler below to ignore the
first data abort to work around this problem.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds the basic support for the Armada 375 SOCs. These SoCs
share most of their IP with the Armada 370/XP SoCs. The main
difference is the use of a Cortex A9 CPU instead of the PJ4B CPU. The
interrupt controller and the L2 cache controller are also different
they are respectively the GIC and the PL310.
The support is introduced in board-v7.c, together with Armada 370/XP,
but a separate DT structure is added, because Armada 375 will need a
different set of SMP operations when the SMP support is introduced.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The system controller block in the Armada 375 has different register
offsets for the system reset and other related functions. Therefore,
this commit introduces the new "armada-375-system-controller"
compatible string to identify the Armada 375 variant of the system
controller.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Until now, the CPU_PJ4B Kconfig option was selected by
MACH_ARMADA_MVEBU, i.e for all Armada MVEBU SOCs. In preparation to
the introduction of Cortex-A9 based Armada MVEBU SOCs, this selection
is moved down to the Armada 370 and Armada XP specific options.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Due to a mistake made when merging Armada 370 and Armada XP DT machine
structures, the name of the structure was incorrectly chosen as being
ARMADA_XP_DT, while the structure also covers Armada 370. Therefore,
we rename the structure to ARMADA_370_XP_DT.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In preparation to the introduction of the support of Armada 375 and
Armada 38x, this commit renames arch/arm/mach-mvebu/armada-370-xp.c to
arch/arm/mach-mvebu/board-v7.c. The board-v7.c name as we expect this
file to ultimately contain the DT_MACHINE_START definitions for all
ARMv7 Marvell EBU platforms (370, 375, 38x, XP and Dove as of today).
In relation to this file rename, this commit also:
* Renames the hidden Kconfig symbol MACH_ARMADA_370_XP to
MACH_MVEBU_V7. This hidden symbol is selected by the various
per-SoC visible Kconfig options to trigger the build of board-v7.c.
* Renames a certain number of functions in board-v7.c so that their
armada_370_xp prefix is replaced by a mvebu prefix. The .dt_compat
array keeps its armada_370_xp prefix because the new SOCs will be
introduced with separate .dt_compat arrays, due to the need for
different SMP operations.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
- kirkwood
- new board QNAP 419
- new board Excito Bubba B3
- mvebu
- use gpio and input defines for Armada 370/XP boards
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Merge tag 'mvebu-dt-3.15' of git://git.infradead.org/linux-mvebu into next/dt
Merge "mvebu DT changes for v3.15" from Jason Cooper:
- kirkwood
- new board QNAP 419
- new board Excito Bubba B3
- mvebu
- use gpio and input defines for Armada 370/XP boards
* tag 'mvebu-dt-3.15' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: use input DT defines in Armada 370/XP boards
ARM: mvebu: use GPIO DT defines in Armada 370/XP boards
ARM: Kirkwood: Add DT description of QNAP 419
ARM: Kirkwood: Add support for Excito Bubba B3
Signed-off-by: Olof Johansson <olof@lixom.net>
DT nodes that contain a reg property should include a unit address in
their name. Add the missing unit addresses.
The unit address in a node name must match the value in the reg property.
Fix the cases where they don't match.
Don't fix the /clocks/* node names yet; that causes problems the clock
driver to attempt to register multiple clocks with the same name, which
fails.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
This patch adds support for SATA on Phytec phyFLEX-i.MX6 Quad module.
Signed-off-by: Ashutosh singh <ashutosh.s@phytec.in>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds support for GPMI-NAND on Phytec phyFLEX-i.MX6 Quad module.
Signed-off-by: Ashutosh singh <ashutosh.s@phytec.in>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds support for USB_HOST on Phytec phyFLEX-i.MX6 Quad module.
Signed-off-by: Ashutosh singh <ashutosh.s@phytec.in>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds support for USB_OTG on Phytec phyFLEX-i.MX6 Quad module.
Signed-off-by: Ashutosh singh <ashutosh.s@phytec.in>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The compatible property should be m41t62, not mt41t62, so fix this.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add the necessary DT node to probe the rng driver on
msm8960-cdp platform.
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Tested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Add the necessary DT node to probe the rng driver on
msm8974 platforms.
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Add the necessary nodes to support SMP on MSM8660, MSM8960, and
MSM8974/APQ8074. While we're here also add in the error
interrupts for the Krait cache error detection.
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
[sboyd: Split into separate patch, add error interrupts]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
pin-related configuration from the Ux500 board files.
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Merge tag 'ab8500-dt-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt
Merge "Ux500 DT conversion" from Linus Walleij:
AB8500 device tree conversion and the deletion of all pin-related
configuration from the Ux500 board files.
* tag 'ab8500-dt-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: move last AB8505 set-up to DT
ARM: ux500: move AB8500 clock out pins to DT
ARM: ux500: move AB8500 modem I2C settings to DT
ARM: ux500: move AB8500 EXTCPENA from board file to DT
ARM: ux500: move AB8500 DMIC settings to DT
ARM: ux500: move AB8500 USB UICC settings to DT
ARM: ux500: move AB8500 audio interface 1 settings to DT
ARM: ux500: move AB8500 PWM out settings to device tree
ARM: ux500: move AB8500 YCBCR settings to device tree
ARM: ux500: move AB8500 GPIOs to device tree
Signed-off-by: Olof Johansson <olof@lixom.net>
- New SoC device tree support for imx35 and imx50
- A good number of new board support: imx25-eukrea, imx28-duckbill,
imx28-eukrea, Eukrea cpuimx35, imx50-evk, imx51-eukrea, imx53-voipac,
MCIMX53-START-R and Ka-Ro TX53.
- Quite some updates and tweaking on imx27 phycore and apf27dev boards
- Add pinfunc headers for imx25, imx27 and imx50
- Make pinctrl nodes board specific to avoid floating board specific
device tree blob with so many unused pinctrl data
- Use generic node name for fixed regulator
- Use clock defines in imx5 DTS files
- Use macros for interrupt and gpio flags
- A plenty of random updates on various SoC and board device tree
sources, adding pinctrl settings, device nodes, properties, aliases.
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Merge tag 'imx-dt-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
Merge "i.MX device tree changes for 3.15" from Shawn Guo:
- New SoC device tree support for imx35 and imx50
- A good number of new board support: imx25-eukrea, imx28-duckbill,
imx28-eukrea, Eukrea cpuimx35, imx50-evk, imx51-eukrea, imx53-voipac,
MCIMX53-START-R and Ka-Ro TX53.
- Quite some updates and tweaking on imx27 phycore and apf27dev boards
- Add pinfunc headers for imx25, imx27 and imx50
- Make pinctrl nodes board specific to avoid floating board specific
device tree blob with so many unused pinctrl data
- Use generic node name for fixed regulator
- Use clock defines in imx5 DTS files
- Use macros for interrupt and gpio flags
- A plenty of random updates on various SoC and board device tree
sources, adding pinctrl settings, device nodes, properties, aliases.
* tag 'imx-dt-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6: (89 commits)
ARM: dts: imx28-m28cu3: Remove 'reset-active-high'
ARM: dts: imx5: use imx51-ssi
ARM: dts: imx51: Add mmc aliases
ARM: dts: imx53: Add mmc aliases
ARM: dts: imx53: add support for Ka-Ro TX53 modules
ARM: dts: Add support for the cpuimx35 board from Eukrea and its baseboard.
ARM: dts: imx28-apf28dev: add user button
ARM: dts: i.MX51: Switch to use standard definitions for input subsystem
ARM: dts: i.MX53: add support for MCIMX53-START-R
ARM: dts: i.MX53: move common QSB nodes to new file
ARM: dts: imx53-evk: Remove board support
ARM: dts: vf610: use the interrupt macros
ARM: dts: imx53: Add gpio and input dt includes.
ARM: dts: i.MX27: Add SSI nodes
ARM: dts: mxs: add mxs phy controller id
ARM: dts: imx27-phytec-phycore-rdk: Add pinctrl definitions for WEIM
ARM: dts: imx27-phytec-phycore-rdk: Add pingrp for SDHC
ARM: dts: imx27-phytec-phycore-som: Add spi-cs-high property to PMIC
ARM: dts: imx27-phytec-phycore-rdk: Enable 1-Wire module
ARM: dts: imx27-phytec-phycore-som: Add NFC pin group
...
- A good number of new i.MX6 boards support: cm-fx6, dmo-edmqmx6,
nitrogen6x, Gateworks Ventana gw5xxx family, DFI FS700-M60 and
Zealz GK802
- Update imx6q-sabrelite device tree and add Dual Lite/Solo support
- Move pins that are used by particular client device out of hog group
- Use GPIO_6 for FEC interrupt to workaround a hardware bug (ERR006687
ENET: Only the ENET wake-up interrupt request can wake the system
from Wait mode.)
- Make pinctrl nodes board specific to avoid floating board specific
device tree blob with so many unused pinctrl data
- Use generic node name for fixed regulator
- Update OPP table for cpufreq support
- Random updates on various board device tree sources, adding pinctrl
settings, device nodes, properties, etc.
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Merge tag 'imx6-dt-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
Merge "i.MX6 device tree changes for 3.15" from Shawn Guo:
- A good number of new i.MX6 boards support: cm-fx6, dmo-edmqmx6,
nitrogen6x, Gateworks Ventana gw5xxx family, DFI FS700-M60 and
Zealz GK802
- Update imx6q-sabrelite device tree and add Dual Lite/Solo support
- Move pins that are used by particular client device out of hog group
- Use GPIO_6 for FEC interrupt to workaround a hardware bug (ERR006687
ENET: Only the ENET wake-up interrupt request can wake the system
from Wait mode.)
- Make pinctrl nodes board specific to avoid floating board specific
device tree blob with so many unused pinctrl data
- Use generic node name for fixed regulator
- Update OPP table for cpufreq support
- Random updates on various board device tree sources, adding pinctrl
settings, device nodes, properties, etc.
* tag 'imx6-dt-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6: (62 commits)
ARM: dts: imx6q: Add support for Zealz GK802
ARM: dts: imx6: Add DFI FS700-M60 board support
ARM: dts: imx6: use imx51-ssi
ARM: dts: imx6qdl: Add mmc aliases
ARM: dts: imx6q: Add spi4 alias
ARM: dts: imx6qdl-sabreauto: Add LVDS support
ARM: dts: imx6sl: add keypad support for i.mx6sl-evk board.
ARM: dts: imx6sl: add ocram device support
ARM: dts: imx6qdl: enable dma for spi
ARM: dts: imx6qdl-sabresd: Add PFUZE100 support
ARM: dts: imx6: add mxs phy controller id
ARM: dts: imx6: add anatop phandle for usbphy
ARM: dts: imx6q-arm2: use GPIO_6 for FEC interrupt.
ARM: dts: imx6qdl-sabreauto: use GPIO_6 for FEC interrupt.
ARM: dts: imx6qdl-sabrelite: use GPIO_6 for FEC interrupt.
ARM: dts: imx6qdl: use interrupts-extended for fec
ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ
ARM: dts: imx6q-sabrelite: PHY reset is active-low
ARM: dts: imx6: Use 'vddarm' as the regulator name
ARM: dts: imx6qdl-sabresd: Add power key support
...
* r8a7791 (R-Car M2) based Koelsch board
- Enable GPIO Keys, (1+1)GiB memory, SATA0 and serial ports
- Add VIN and thermal clocks
- Remove r8a7791-koelsch-reference.dts
* r8a7790 (R-Car H2) based Lager board
- Replace IRQ type numerical values with macros
- Enable SATA0 and serial ports
- Add VIN and thermal clocks
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Merge tag 'renesas-dt-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Merge "Renesas ARM Based SoC DT Updates for v3.15" from Simon Horman:
* r8a7791 (R-Car M2) based Koelsch board
- Enable GPIO Keys, (1+1)GiB memory, SATA0 and serial ports
- Add VIN and thermal clocks
- Remove r8a7791-koelsch-reference.dts
* r8a7790 (R-Car H2) based Lager board
- Replace IRQ type numerical values with macros
- Enable SATA0 and serial ports
- Add VIN and thermal clocks
* tag 'renesas-dt-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7790: Replace IRQ type numerical values with macros
ARM: shmobile: r8a7790: Fix serial ports DT compatible strings
ARM: shmobile: lager: Enable SATA1 in r8a7790-lager.dts
ARM: shmobile: r8a7790: Add SATA nodes to r8a7790.dtsi
ARM: shmobile: koelsch: Enable SATA0 in r8a7791-koelsch.dts
ARM: shmobile: r8a7791: Add SATA nodes to r8a7791.dtsi
ARM: shmobile: r8a7791: Add SATA clocks to device tree
ARM: shmobile: r8a7790: Add SATA clocks to device tree
ARM: shmobile: r8a7791: Add VIN clocks to device tree
ARM: shmobile: r8a7790: Add VIN clocks to device tree
ARM: shmobile: r8a7790: Add serial ports to the device tree
ARM: shmobile: r8a7791: Add serial ports to the device tree
ARM: shmobile: r8a7790: Add thermal clock in device tree
ARM: shmobile: r8a7791: Add thermal clock in device tree
ARM: shmobile: koelsch: (1+1)GiB memory in DT
ARM: shmobile: Add GPIO keys to Koelsch DTS
ARM: shmobile: dts: Remove r8a7791-koelsch-reference.dts
Signed-off-by: Olof Johansson <olof@lixom.net>
On imx6sl-evk board the VGEN1 regulator powers up the NVCC_1P2V domain of the
imx6sl SoC, so we need to keep it always powered.
According to imx6sl datasheet the GPIO block has three supplies:
NVCC33_IO, NVCC18_IO and NVCC_1P2V and it states that:
"All digital I/O supplies (NVCC_xxxx) must be powered under normal conditions
whether the associated I/O pins are in use or not"
This problem has been observed by the fact that a GPIO connected to an LED could
not work when the PMIC driver was enabled.
Keeping VGEN1 regulator always enabled fixes the problem.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The D9 LED controlled by gpio on the imx6qdl-sabreauto
CPU board is a debug LED according to the board design.
This patch adds the relevant device tree nodes to the
imx6qdl-sabreauto device tree file to support this LED.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds and enables simple-card support in DT node.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
In commit f0402f9b47 ("ARM: ixp4xx: stop using <mach/timex.h>")
I didn't intend to implement a functional change, but as Olof noticed I
failed---at least a bit. Before this commit the following was used to
determine the latch value used:
#define IXP4XX_TIMER_FREQ 66666000
#define CLOCK_TICK_RATE \
(((IXP4XX_TIMER_FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
#define LATCH ((CLOCK_TICK_RATE + HZ/2) / HZ)
The complicated calculation was done "b/c the timer register ignores the
bottom 2 bits of the LATCH value." With HZ=100 CLOCK_TICK_RATE used to
calculate to 66666100 and so LATCH to 666661. In ixp4xx_set_mode the
term
LATCH & ~IXP4XX_OST_RELOAD_MASK
was used to write to the relevant register (with IXP4XX_OST_RELOAD_MASK
being 3) and so effectively 666660 was used.
In commit f0402f9b47 I translated that to:
#define IXP4XX_TIMER_FREQ 66666000
#define IXP4XX_LATCH DIV_ROUND_CLOSEST(IXP4XX_TIMER_FREQ, HZ)
which results in the same register writes, but still doesn't bear in
mind that the two least significant bits cannot be specified (which is
relevant only when HZ or IXP4XX_TIMER_FREQ are changed).
Instead of reverting back to the old approach use a more obvious and
also more correct way to calculate LATCH. (Regarding the more
correct claim: With IXP4XX_TIMER_FREQ == 66665999, the old code resulted
in LATCH = 666657 corresponding to a cycle time of 0.009999940149400597
seconds (error: -6.0e-8 s) while the new approach results in LATCH =
666660 and so a cycle time of 0.010000000150001503 seconds
(error: 1.5e-10 s).)
Fixes: f0402f9b47 ("ARM: ixp4xx: stop using <mach/timex.h>")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
At late init all unused clocks are disabled. So clocks that were not
get before will be gated. In Keysone 2 SoC we have at least one
necessary clock that is not used by any driver - "msmcsram". This
clock is necessary, because it supplies the Multicore Shared Memory
Controller (MSMC). MSMC is the coherency interconnect and all the
coherent masters are connected to it including devices which are not
under Linux OS control. MSMC clock should not be touched even in low
power states.
So drop the clock node, otherwise 'clk_ignore_unused' parameter will
disable the clock leading to system stall.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
The corresponding driver didn't make it into v3.14, so we need to remove
the node. Dove systems fail to boot with the node present and no
driver.
This node will be re-added when the driver makes it to mainline.
Reported-by: Jean-Francois Moine <moinejf@free.fr>
Tested-by: Jean-Francois Moine <moinejf@free.fr>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Switch the device tree to the new compatibles introduced in the clock drivers
to have a common pattern accross all Allwinner SoCs.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Allwinner A20 SoC is built around a pair of Cortex-A7 cores,
which have the usual generic timers. Report this in the DT.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Activate the shiny new riic driver for i2c2. Tested by accessing the
eeprom on the genmai board.
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Magnus Damm <damm@opensource.se>
[horms+renesas@verge.net.au: resolved conflict]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Armada 385 DB board is the development board from Marvell for the
Armada 385 SoC. This commit adds a Device Tree description for this
board, which enables the following features:
* Network interfaces
* I2C buses
* SDIO
* Serial port
* SPI bus, with a SPI flash
* PCIe interfaces
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 380 and 385 SoCs are new SoCs from Marvell, based on a
Cortex-A9 cores (single core for 380, dual core for 385) and a number
of hardware blocks that are common with earlier SoCs from the mvebu
family.
The provided Device Tree describes the following parts of the SoC:
* CPU
* Device Bus
* Clocks
* Interrupt controllers: GIC and MPIC
* GPIO controllers
* I2C buses
* L2 cache
* MBus controller
* Pinctrl
* Serial
* SPI buses
* System controller (for reboot)
* Timer
* XOR engines
* PCIe controllers
* Network interfaces
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 375 DB board is the development board from Marvell for the
Armada 375 SoC. This commit adds a Device Tree description for this
board, which enables the following features:
* I2C buses
* SDIO
* Serial port
* SPI bus, with a SPI flash. Note that the SPI bus is disabled by
default, because it conflicts with the NAND, and can only work if
the board boots out of SPI. Since most boards are shipped to boot
out of NAND, we're default to having the SPI bus disabled.
* PCIe interfaces
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 375 SoC is a new SoC from Marvell, based on a dual core
Cortex-A9 and a number of hardware blocks that are common with earlier
SoCs from the mvebu family.
The provided Device Tree describes the following parts of the SoC:
* CPUs
* Device Bus
* Clocks
* Interrupt controllers: GIC and MPIC
* GPIO controllers
* I2C buses
* L2 cache
* MBus controller
* SDIO
* Pinctrl
* SATA
* Serial
* SPI buses
* System controller (for reboot)
* Timer
* XOR engines
* PCIe controllers
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Andrew Lunn