Commit Graph

38 Commits

Author SHA1 Message Date
David Howells 3b139cdb37 Blackfin: Rename IRQ flags handling functions
Rename h/w IRQ flags handling functions to be in line with what is expected for
the irq renaming patch.  This renames local_*_hw() to hard_local_*() using the
following perl command:

	perl -pi -e 's/local_irq_(restore|enable|disable)_hw/hard_local_irq_\1/ or s/local_irq_save_hw([_a-z]*)[(]flags[)]/flags = hard_local_irq_save\1()/' `find arch/blackfin/ -name "*.[ch]"`

and then fixing up asm/irqflags.h manually.

Additionally, arch/hard_local_save_flags() and arch/hard_local_irq_save() both
return the flags rather than passing it through the argument list.

Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-07 14:08:52 +01:00
Mike Frysinger 1ed181f248 Blackfin: move MPU anomaly check to common location
Keep all anomaly/arch checks in one place to keep logic simple.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-08-06 12:55:45 -04:00
Barry Song 726e96561e Blackfin: respect the L1 kconfig optimization in the MPU code
Restore support for CONFIG_EXCPT_IRQ_SYSC_L1 in the MPU CPLB manager.

Signed-off-by: Barry Song <barry.song@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-03-09 00:30:49 -05:00
Barry Song d86bfb1600 Blackfin: initial XIP support
Signed-off-by: Barry Song <barry.song@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-03-09 00:30:48 -05:00
Sonic Zhang 5792ab2a0a Blackfin: MPU: handle caches for reserved memory
We weren't handling the user-specified cache behavior for the reserved
memory regions (via mem=/max_mem=).  The no-MPU code already takes care
of this, so add support to the MPU code as well.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-03-09 00:30:46 -05:00
Barry Song e18e7dd334 Blackfin: fix MPU page permission masks overflow when dealing with async memory
Attempting to use the MPU while doing XIP out of parallel flash hooked up
to the async memory bus would often result in random crashes as the MPU
slowly corrupted memory.

The fallout here is that the async banks gain MPU protection from user
space too.  So any accesses have to go through the mmap() interface rather
than just using hardcoded pointers.

Signed-off-by: Barry Song <barry.song@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-03-09 00:30:46 -05:00
Mike Frysinger 0a68b5341d Blackfin: MPU: add missing __init markings
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-12-15 00:16:53 -05:00
Barry Song e187837b6f Blackfin: MPU: support XIP in async flash memory
The NOMPU code already supported executing in the async banks, so this
brings the MPU code in line.

Signed-off-by: Barry Song <barry.song@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-12-15 00:15:54 -05:00
André Goddard Rosa 7bae2c4898 Blackfin: fix cache Kconfig typo
The Kconfig option is "BFIN_EXTMEM_WRITETHROUGH", not "..._WRITETROUGH".

Signed-off-by: André Goddard Rosa <andre.goddard@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-11-25 02:35:35 -05:00
Robin Getz 96f1050d3d Blackfin: mass clean up of copyright/licensing info
Bill Gatliff & David Brownell pointed out we were missing some
copyrights, and licensing terms in some of the files in
./arch/blackfin, so this fixes things, and cleans them up.

It also removes:
 - verbose GPL text(refer to the top level ./COPYING file)
 - file names (you are looking at the file)
 - bug url (it's in the ./MAINTAINERS file)
 - "or later" on GPL-2, when we did not have that right

It also allows some Blackfin-specific assembly files to be under a BSD
like license (for people to use them outside of Linux).

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-10-07 04:36:26 -04:00
Mike Frysinger ea426e6c62 Blackfin: unify cache init functions
The CPLB implementations (mpu/nompu) had exact copies of the cacheinit
code.  Even the i/d cache functions are largely the same.  So unify them
both in the common kernel cache code.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-16 22:10:49 -04:00
Yi Li b6dbde27dd Blackfin: use raw_smp_processor_id() in exception code
When preempt debugging is enabled, smp_processor_id() may utilize the
"current" structure.  This may not be safe to access under all exceptions
due to it being in dynamically allocated memory.  So in exception code,
make sure we use raw_smp_processor_id() instead to get at the real value
directly.

Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-16 22:10:32 -04:00
Yi Li eb7bd9c461 Blackfin: cleanup sync handling when enabling/disabling cplbs
The handling of updating the [DI]MEM_CONTROL MMRs does not follow proper
sync procedures as laid out in the Blackfin programming manual.  So rather
than audit/fix every call location, create helper functions that do the
right things in order to safely update these MMRs.  Then convert all call
sites to use these new helper functions.

While we're fixing the code, drop the workaround for anomaly 05000125 as
that anomaly applies to old versions of silicon that we do not support.

Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-16 22:10:19 -04:00
Jie Zhang 41ba653f24 Blackfin: decouple unrelated cache settings to get exact behavior
The current cache options don't really represent the hardware features.
They end up setting different aspects of the hardware so that the end
result is to turn on/off the cache.  Unfortunately, when we hit cache
problems with the hardware, it's difficult to test different settings to
root cause the problem.  The current settings also don't cleanly allow for
different caching behaviors with different regions of memory.

So split the configure options such that they properly reflect the settings
that are applied to the hardware.

Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-06-22 21:15:59 -04:00
Jie Zhang 67834fa93d Blackfin: rename bfin_addr_dcachable to bfin_addr_dcacheable
The latter naming convention is much more common.

Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-06-13 07:20:06 -04:00
Robin Getz a17c7f6f5b Blackfin: make sure MPU CPLB for first 1k is marked as valid
This way we properly catch and kill applications that jump to a NULL ptr.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-06-12 06:11:40 -04:00
Graf Yang e522c8466d Blackfin: work around anomaly 05000287
Make sure we work around anomaly 05000287 by configuring different port
preferences for the data cache.

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-06-12 06:11:31 -04:00
Bernd Schmidt bf324cb81a Blackfin arch: fix bug - traps test case 19 for exception 0x2d fails
Enable null pointer checking for ICPLBs. The code was there but for
some reason I had commented it out at some stage during development.

Should restrict this to 1K since atomic ops start there.

Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2009-02-04 16:49:45 +08:00
Yi Li 6a01f23033 Blackfin arch: merge adeos blackfin part to arch/blackfin/
[Mike Frysinger <vapier.adi@gmail.com>:
 - handle bf531/bf532/bf534/bf536 variants in ipipe.h
 - cleanup IPIPE logic for bfin_set_irq_handler()
 - cleanup ipipe asm code a bit and add missing ENDPROC()
 - simplify IPIPE code in trap_c
 - unify some of the IPIPE code and fix style
 - simplify DO_IRQ_L1 handling with ipipe code
 - revert IRQ_SW_INT# addition from ipipe merge
 - remove duplicate get_{c,s}clk() prototypes
]

Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2009-01-07 23:14:39 +08:00
Bernd Schmidt dbdf20db53 Blackfin arch: Faster C implementation of no-MPU CPLB handler
This is a mixture ofcMichael McTernan's patch and the existing cplb-mpu code.

We ditch the old cplb-nompu implementation, which is a good example of
why a good algorithm in a HLL is preferrable to a bad algorithm written in
assembly.  Rather than try to construct a table of all posible CPLBs and
search it, we just create a (smaller) table of memory regions and
their attributes.  Some of the data structures are now unified for both
the mpu and nompu cases.  A lot of needless complexity in cplbinit.c is
removed.

Further optimizations:
  * compile cplbmgr.c with a lot of -ffixed-reg options, and omit saving
    these registers on the stack when entering a CPLB exception.
  * lose cli/nop/nop/sti sequences for some workarounds - these don't
  * make
    sense in an exception context

Additional code unification should be possible after this.

[Mike Frysinger <vapier.adi@gmail.com>:
 - convert CPP if statements to C if statements
 - remove redundant statements
 - use a do...while loop rather than a for loop to get slightly better
   optimization and to avoid gcc "may be used uninitialized" warnings ...
   we know that the [id]cplb_nr_bounds variables will never be 0, so this
   is OK
 - the no-mpu code was the last user of MAX_MEM_SIZE and with that rewritten,
   we can punt it
 - add some BUG_ON() checks to make sure we dont overflow the small
   cplb_bounds array
 - add i/d cplb entries for the bootrom because there is functions/data in
   there we want to access
 - we do not need a NULL trailing entry as any time we access the bounds
   arrays, we use the nr_bounds variable
]

Signed-off-by: Michael McTernan <mmcternan@airvana.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2009-01-07 23:14:38 +08:00
Graf Yang dbc895f955 Blackfin arch: smp patch cleanup from LKML review
1. Use inline get_l1_... functions instead of macro
2. Fix compile issue about smp barrier functions

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2009-01-07 23:14:39 +08:00
Mike Frysinger ff4c02e4be Blackfin arch: unify cplbinfo files
Merge MPU and noMPU version of CPLB info code to one common version.

Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-11-18 17:48:22 +08:00
Graf Yang b8a989893c Blackfin arch: SMP supporting patchset: Blackfin CPLB related code
Blackfin dual core BF561 processor can support SMP like features.
https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like

In this patch, we provide SMP extend to Blackfin CPLB related code

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-11-18 17:48:22 +08:00
Mike Frysinger a92946bc6a Blackfin arch: use the new bfin_addr_dcachable() function
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-10-16 23:25:34 +08:00
Sonic Zhang f099f39acf Blackfin arch: Make L2 SRAM cacheable
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-10-09 14:11:57 +08:00
Graf Yang 5b04f271fe Blackfin arch: Modify some funtion names to more genernal ones
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-10-08 17:32:57 +08:00
Bernd Schmidt 5d2e321306 Blackfin arch: fixing bug - under IRQ stress, running applications may wrongly trigger an ICPLB miss and be killed
Disable IRQs while frobbing the CPLB registers, to avoid accessing the
data in current_rwx_mask while it isn't covered by CPLBs.

Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-10-07 16:27:01 +08:00
Mike Frysinger 9216bbc838 Blackfin arch: mark some functions as __init as they are only called from __init functions
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-08-14 14:35:20 +08:00
Bernd Schmidt 00d205a1ce [Blackfin] arch: lose unnecessary dependency on CONFIG_BFIN_ICACHE for MPU
Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-04-25 03:26:48 +08:00
Mike Frysinger 4bea8b20fd [Blackfin] arch: add implicit icplb for the bootrom so we can use the utility functions in the kernel
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-04-24 07:23:36 +08:00
Mike Frysinger 4e354b5499 [Blackfin] arch: cplb-mpu code clean up
- allow bootrom to be readable from supervisor mode
 - delete unused local variable "addr"
 - punt unused local defines of cplbinfo.c

Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-04-24 05:44:32 +08:00
Mike Frysinger 8cab0288c6 [Blackfin] arch: add boot messages to quickly distinguish between MPU/NOMPU settings
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-04-24 05:13:10 +08:00
Bernd Schmidt 1ebc723cf0 [Blackfin] arch: support the reserved memory region in the MPU code
Pointed-out-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-04-24 02:58:26 +08:00
Bernd Schmidt d56daae9be [Blackfin] arch: fix bug - a crash on bootup with CONFIG_MPU on the BF548
The function flush_switched_dcplbs was clearing the CPLB entries covering
the process permission bitmasks.  This means that the sequence

	flush_switched_dcplbs ();
        set_mask_dcplbs(mm->context.page_rwx_mask);

has a problem: if kernel code (such as an interrupt) causes a CPLB miss before
set_mask_dcplbs completes, the CPLB handler function causes a double fault,
with an instantaneous reboot.

This bug fix is dedicated to Michael Hennerich, the only person in the world
capable of providing working JTAG hardware.

Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-04-24 02:56:36 +08:00
Bernd Schmidt b4bb68f7d0 [Blackfin] arch: fix bug - Make the MPU code aware of the async banks and the uncached DMA area.
Bug: CONFIG_MPU doesn't seem to handle access to ASYNC/IO Memory well
http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3912

Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-04-23 07:26:23 +08:00
Bernd Schmidt dbfe44f02b [Blackfin] arch: fix up - CONFIG_BLKFIN_WT was renamed CONFIG_BFIN_WT while the MPU code was out-of-tree.
Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-04-23 07:11:55 +08:00
Mike Frysinger c605999bd9 [Blackfin] arch: error out if ANOMALY_05000263 applies while enabling the MPU
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2008-02-02 12:28:23 +08:00
Bernd Schmidt b97b8a9983 [Blackfin] arch: Initial checkin of the memory protection support.
Enable it with CONFIG_MPU.

Signed-off-by: Bernd Schmidt <bernd.schmidt@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2008-01-27 18:39:16 +08:00