Commit Graph

187 Commits

Author SHA1 Message Date
Dan Williams 105ef9a0af [ARM] 3942/1: ARM: comment: consistent_sync should not be called directly
/*
 * Note: Drivers should NOT use this function directly, as it will break
 * platforms with CONFIG_DMABOUNCE.
 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
 */

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-11-22 22:45:57 +00:00
Ray Lehtiniemi 5e70982750 [ARM] 3927/1: Allow show_mem() to work with holes in memory map.
show_mem() was not correctly handling holes in the memory
map.  It was treating the freed sections of the map as
though they contained valid struct page entries.  This
could cause incorrect debugging output or even a kernel
panic.

This patch keeps the struct meminfo around after system
initialization so that show_mem() can use it when
scanning memory.  show_mem() now walks over each bank
of each online node, rather than assuming that each node
contains a single contiguous bank.

Signed-off-by: Ray Lehtiniemi <rayl@mail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-11-07 19:39:00 +00:00
Paul Gortmaker 8f7f9435e6 [ARM] 3912/1: Make PXA270 advertise HWCAP_IWMMXT capability
ARM patch 3756/1 added HWCAP_IWMMXT.  This patch adds support
for broadcasting that info via /proc/cpuinfo and sets it for
the CPU features of the PXA270.

I've booted 19rc3 on a pxa270 and confirmed that the /proc/cpuinfo
shows "iwmmxt" in the Features.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-11-02 22:58:53 +00:00
Al Viro 1622605cf6 [PATCH] arm: it's OK to pass pointer to volatile as iounmap() argument...
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-10-08 18:50:58 -07:00
Linus Torvalds 63c422afe3 Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 3848/1: pxafb: Add option of fixing video modes and spitz QVGA mode support
  [ARM] 3880/1: remove the last trace of iop31x support
  [ARM] 3879/1: ep93xx: instantiate platform devices for ep93xx ethernet
  [ARM] 3809/3: get rid of 4 megabyte kernel image size limit
  [ARM] Fix XIP_KERNEL build error in arch/arm/mm/mmu.c
  [ARM] 3874/1: Remove leftover usage of asm/timeofday.h
2006-10-03 09:14:00 -07:00
Russell King 6ae5a6ef03 [ARM] Fix XIP_KERNEL build error in arch/arm/mm/mmu.c
XIP kernels need to know the start/end of text, but we were
missing the declaration of _etext in mmu.c.  Add it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-30 10:50:05 +01:00
Sukadev Bhattiprolu f400e198b2 [PATCH] pidspace: is_init()
This is an updated version of Eric Biederman's is_init() patch.
(http://lkml.org/lkml/2006/2/6/280).  It applies cleanly to 2.6.18-rc3 and
replaces a few more instances of ->pid == 1 with is_init().

Further, is_init() checks pid and thus removes dependency on Eric's other
patches for now.

Eric's original description:

	There are a lot of places in the kernel where we test for init
	because we give it special properties.  Most  significantly init
	must not die.  This results in code all over the kernel test
	->pid == 1.

	Introduce is_init to capture this case.

	With multiple pid spaces for all of the cases affected we are
	looking for only the first process on the system, not some other
	process that has pid == 1.

Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
Signed-off-by: Sukadev Bhattiprolu <sukadev@us.ibm.com>
Cc: Dave Hansen <haveblue@us.ibm.com>
Cc: Serge Hallyn <serue@us.ibm.com>
Cc: Cedric Le Goater <clg@fr.ibm.com>
Cc: <lxc-devel@lists.sourceforge.net>
Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-09-29 09:18:12 -07:00
Jason Baron df67b3daea [PATCH] make PROT_WRITE imply PROT_READ
Make PROT_WRITE imply PROT_READ for a number of architectures which don't
support write only in hardware.

While looking at this, I noticed that some architectures which do not
support write only mappings already take the exact same approach.  For
example, in arch/alpha/mm/fault.c:

"
        if (cause < 0) {
                if (!(vma->vm_flags & VM_EXEC))
                        goto bad_area;
        } else if (!cause) {
                /* Allow reads even for write-only mappings */
                if (!(vma->vm_flags & (VM_READ | VM_WRITE)))
                        goto bad_area;
        } else {
                if (!(vma->vm_flags & VM_WRITE))
                        goto bad_area;
        }
"

Thus, this patch brings other architectures which do not support write only
mappings in-line and consistent with the rest.  I've verified the patch on
ia64, x86_64 and x86.

Additional discussion:

Several architectures, including x86, can not support write-only mappings.
The pte for x86 reserves a single bit for protection and its two states are
read only or read/write.  Thus, write only is not supported in h/w.

Currently, if i 'mmap' a page write-only, the first read attempt on that page
creates a page fault and will SEGV.  That check is enforced in
arch/blah/mm/fault.c.  However, if i first write that page it will fault in
and the pte will be set to read/write.  Thus, any subsequent reads to the page
will succeed.  It is this inconsistency in behavior that this patch is
attempting to address.  Furthermore, if the page is swapped out, and then
brought back the first read will also cause a SEGV.  Thus, any arbitrary read
on a page can potentially result in a SEGV.

According to the SuSv3 spec, "if the application requests only PROT_WRITE, the
implementation may also allow read access." Also as mentioned, some
archtectures, such as alpha, shown above already take the approach that i am
suggesting.

The counter-argument to this raised by Arjan, is that the kernel is enforcing
the write only mapping the best it can given the h/w limitations.  This is
true, however Alan Cox, and myself would argue that the inconsitency in
behavior, that is applications can sometimes work/sometimes fails is highly
undesireable.  If you read through the thread, i think people, came to an
agreement on the last patch i posted, as nobody has objected to it...

Signed-off-by: Jason Baron <jbaron@redhat.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: "Luck, Tony" <tony.luck@intel.com>
Cc: Hugh Dickins <hugh@veritas.com>
Cc: Roman Zippel <zippel@linux-m68k.org>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Andi Kleen <ak@muc.de>
Acked-by: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Cc: Kazumoto Kojima <kkojima@rr.iij4u.or.jp>
Cc: Ian Molton <spyro@f2s.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-09-29 09:18:05 -07:00
Linus Torvalds ebdea46fec Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (130 commits)
  [ARM] 3856/1: Add clocksource for Intel IXP4xx platforms
  [ARM] 3855/1: Add generic time support
  [ARM] 3873/1: S3C24XX: Add irq_chip names
  [ARM] 3872/1: S3C24XX: Apply consistant tabbing to irq_chips
  [ARM] 3871/1: S3C24XX: Fix ordering of EINT4..23
  [ARM] nommu: confirms the CR_V bit in nommu mode
  [ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores.
  [ARM] 3870/1: AT91: Start removing static memory mappings
  [ARM] 3869/1: AT91: NAND support for DK and KB9202 boards
  [ARM] 3868/1: AT91 hardware header update
  [ARM] 3867/1: AT91 GPIO update
  [ARM] 3866/1: AT91 clock update
  [ARM] 3865/1: AT91RM9200 header updates
  [ARM] 3862/2: S3C2410 - add basic power management support for AML M5900 series
  [ARM] kthread: switch arch/arm/kernel/apm.c
  [ARM] Off-by-one in arch/arm/common/icst*
  [ARM] 3864/1: Refactore sharpsl_pm
  [ARM] 3863/1: Add Locomo SPI Device
  [ARM] 3847/2:  Convert LOMOMO to use struct device for GPIOs
  [ARM] Use CPU_CACHE_* where possible in asm/cacheflush.h
  ...
2006-09-28 14:40:39 -07:00
Hyok S. Choi 6afd6fae1d [ARM] nommu: confirms the CR_V bit in nommu mode
In nommu mode, the exception vector location depends on the platforms.
Some of the implementations may have some special exception control
forwarding method in their ROM/flash and for some of them has its own
re-mapping mechanism by the h/w.

This patch introduces a special configuration CONFIG_CPU_HIGH_VECTOR which
turns on the CR_V bit in nommu mode. The CR_V bit is turned off by default.
This feature depends on CP15 and does not supported by ARM740.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-28 20:17:30 +01:00
Hyok S. Choi 0f45d7f36b [ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores.
There is no FSR/FAR register on no-CP15 or MPU cores. This patch adds a
dummy abort handler which returns zero for the base restored Data Abort
model !CPU_CP15_MMU cores. The abort-lv4t.S is still used with the fix-up
for the base updated Data Abort model cores.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-28 20:15:46 +01:00
Russell King 6b237a355a [ARM] Make !MMU CPUs depend on !MMU
Don't offer non-MMU based CPUs for selection when CONFIG_MMU is
set.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:44:39 +01:00
Hyok S. Choi f37f46eb1c [ARM] nommu: add ARM946E-S core support
This patch adds ARM946E-S core support which has typically 8KB I&D cache.
It has a MPU and supports ARMv5TE instruction set.

Because the ARM946E-S core can be synthesizable with various cache size,
CONFIG_CPU_DCACHE_SIZE is defined for vendor specific configurations.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:39:19 +01:00
Hyok S. Choi d60674eb5d [ARM] nommu: add ARM940T core support
This patch adds ARM940T core support which has 4KB D-cache, 4KB I-cache
and a MPU.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:39:18 +01:00
Hyok S. Choi 43f5f0146e [ARM] nommu: add ARM9TDMI core support
This patch adds ARM9TDMI core support which has no cache and no CP15
register(no memory control unit).

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:39:17 +01:00
Hyok S. Choi b731c3118d [ARM] nommu: add ARM740T core support
This patch adds ARM740T core support which has a MPU and 4KB or 8KB cache.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:39:17 +01:00
Hyok S. Choi 07e0da78ab [ARM] nommu: add ARM7TDMI core support
This patch adds ARM7TDMI core support which has no cache and no CP15
register(no memory control unit).

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:39:17 +01:00
Hyok S. Choi f12d0d7c77 [ARM] nommu: manage the CP15 things
All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:

     Related operation	Safe condition
  a. any CP15 access	!CPU_CP15
  b. alignment trap	CPU_CP15_MMU
  c. D-cache(C-bit)	CPU_CP15
  d. I-cache		CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
				CPU_ARM720 || CPU_ARM740 ||
				CPU_XSCALE || CPU_XSC3 )
  e. alternate vector	CPU_CP15 && !CPU_ARM740
  f. TTB		CPU_CP15_MMU
  g. Domain		CPU_CP15_MMU
  h. FSR/FAR		CPU_CP15_MMU

For example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:34:30 +01:00
Hyok S. Choi fefdaa06cc [ARM] nommu: defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU
By merging of uClinux/ARM, we need to treat various CPU cores which have
MMU, MPU or even none for memory management. The memory management
coprocessors are controlled by CP15 register set and the ARM core family
can be categorized by 5 groups by the register ;
  G-a. CP15 is MMU : 610, 710, 720, 920, 922, 925, 926, 1020, 1020e, 1022,
		v6 and the derivations sa1100, sa110, xscale, xsc3.
  G-b. CP15 is MPU : 740, 940, 946, 996, 1156.
  G-c. CP15 is MPU or MMU : 1026 (selectable by schematic design)
  G-d. CP15 is exist, but nothing for memory managemnt : 966, 968.
  G-e. no-CP15 : 7tdmi, 9tdmi, 9e, 9ej

This patch defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU. Thus the
family can be defined as :
  - CPU_CP15 only : G-d
  - CPU_CP15_MMU(implies CPU_CP15) : G-a, G-c(selectable)
  - CPU_CP15_MPU(implies CPU_CP15) : G-b, G-c(selectable)
  - !CPU_CP15 : G-e

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:28:47 +01:00
Russell King e5beac371a [ARM] do_bad_area() always takes current and current->active_mm
Since do_bad_area() always takes the currently active task and
(supposed to) take the currently active MM, there's no point passing
them to this function.  Instead, obtain references to them inside
do_bad_area().

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 16:13:48 +01:00
Russell King 80878d6c4a [ARM] Add setup_mm_for_reboot() for nommu
Add an empty setup_mm_for_reboot() function for nommu machines.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 15:43:47 +01:00
Russell King 0c668984dd [ARM] Rename mm-armv.c to pgd.c
mm-armv.c now only contains the pgd allocation/freeing code, so
rename it to have a more sensible filename.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 15:40:28 +01:00
Russell King ae8f154129 [ARM] Move rest of MMU setup code from mm-armv.c to mmu.c
If we're going to have mmu.c for code which is specific to the MMU
machines, we might as well move the other MMU initialisation
specific code from mm-armv.c into this new file.  This also allows
us to make some functions static.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 15:38:34 +01:00
Russell King d111e8f964 [ARM] Split ARM MM initialisation for !mmu
Move the MMU specific code from init.c into mmu.c, and add nommu
fixups to nommu.c

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 15:27:33 +01:00
Russell King 456335e207 [ARM] Separate page table manipulation code from bootmem initialisation
nommu does not require the page table manipulation code in the
bootmem initialisation paths.  Move this into separate inline
functions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 10:10:58 +01:00
George G. Davis 4052ebb7a2 [ARM] 3859/1: Fix devicemaps_init() XIP_KERNEL odd 1MiB XIP_PHYS_ADDR translation error
The ARM XIP_KERNEL map created in devicemaps_init() is wrong.
The map.pfn is rounded down to an even 1MiB section boundary
which results in va/pa translations errors when XIP_PHYS_ADDR
starts on an odd 1MiB boundary and this causes the kernel to
hang.  This patch fixes ARM XIP_KERNEL translation errors for
the odd 1MiB XIP_PHYS_ADDR boundary case.

Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 09:35:05 +01:00
Dave McCracken 46a82b2d55 [PATCH] Standardize pxx_page macros
One of the changes necessary for shared page tables is to standardize the
pxx_page macros.  pte_page and pmd_page have always returned the struct
page associated with their entry, while pte_page_kernel and pmd_page_kernel
have returned the kernel virtual address.  pud_page and pgd_page, on the
other hand, return the kernel virtual address.

Shared page tables needs pud_page and pgd_page to return the actual page
structures.  There are very few actual users of these functions, so it is
simple to standardize their usage.

Since this is basic cleanup, I am submitting these changes as a standalone
patch.  Per Hugh Dickins' comments about it, I am also changing the
pxx_page_kernel macros to pxx_page_vaddr to clarify their meaning.

Signed-off-by: Dave McCracken <dmccr@us.ibm.com>
Cc: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-09-26 08:48:51 -07:00
George G. Davis a71ebdfa52 [ARM] 3853/1: Fix flush_ptrace_access() thinko for nonaliasing VIPT cache case
Fix thinko in the flush_ptrace_access() "if (expr)" for the ARM
VIPT non-aliasing cache case.  We only need to flush cache when
VM_EXEC is set in vma->vm_flags but "if (expr) always evaluates
to true on UP systems for the ARM VIPT non-aliasing cache case.

Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-25 10:34:04 +01:00
Lennert Buytenhek 3f7e5815f4 [ARM] 3817/1: iop3xx: split the iop3xx mach into iop32x and iop33x
Split the iop3xx mach type into iop32x and iop33x -- split the config
symbols, and move the code in the mach-iop3xx directory to the mach-iop32x
and mach-iop33x directories.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-25 10:25:36 +01:00
Lennert Buytenhek 197c9444d6 [ARM] 3814/1: move 80200 dma_inv_range() erratum check out of line
On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
clear the dirty bits, which means that if we invalidate a dirty line,
the dirty data can still be written back to memory later on.

To work around this, dma_inv_range() on these two processors is
implemented as dma_flush_range() (i.e. do a clean D-cache line before
doing the invalidate D-cache line.)  For this, we currently have a
processor ID check in xscale_dma_inv_range(), but a better solution
is to add a separate cache_fns and proc_info for A0/A1 80200.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-25 10:25:27 +01:00
Lennert Buytenhek 51635ad282 [ARM] 3813/1: prevent >= 4G /dev/mem mmap()
Prevent userland from mapping in physical address regions >= 4G by
checking for that in valid_mmap_phys_addr_range().

Unfortunately, we cannot override valid_mmap_phys_addr_range() without
also overriding valid_phys_addr_range(), so copy drivers/char/mem.c's
version of valid_phys_addr_range() over to arch/arm/mm/mmap.c as well.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-25 10:25:26 +01:00
Russell King d84b47115a [ARM] Move mmu.c out of the way
Rename mmu.c to context.c - it's the ARMv6 ASID context handling
code rather than generic "mmu" handling code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-20 14:58:35 +01:00
Russell King 1b2e2b73b4 [ARM] Cleanup arch/arm/mm a little
Move top_pmd into arch/arm/mm/mm.h - nothing outside arch/arm/mm
references it.

Move the repeated definition of TOP_PTE into mm/mm.h, as well as
a few function prototypes.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-20 14:58:35 +01:00
Dan Williams 36694a4c22 [ARM] 3780/1: Fix iop321 cpuid
Patch from Dan Williams

commit a6a38a6622 changed the iop321 id to a value that does not work with all platforms.  Change the mask to permit bit 11.  Tested on an iq80321 600Mhz CRB.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-14 17:45:16 +01:00
Catalin Marinas f854d37ab6 [ARM] 3773/1: Add the HWCAP_VFP bit for the ARM926 CPUs
Patch from Catalin Marinas

The ARM926EJ-S CPU has the VFP coprocessor and therefore it should be shown
in the /proc/cpuinfo if CONFIG_VFP is enabled.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-06 19:03:28 +01:00
George G. Davis a188ad2bc7 [ARM] 3762/1: Fix ptrace cache coherency bug for ARM1136 VIPT nonaliasing Harvard caches
Patch from George G. Davis

Resolve ARM1136 VIPT non-aliasing cache coherency issues observed when
using ptrace to set breakpoints and cleanup copy_{to,from}_user_page()
while we're here as requested by Russell King because "it's also far
too heavy on non-v6 CPUs".

NOTES:

1. Only access_process_vm() calls copy_{to,from}_user_page().
2. access_process_vm() calls get_user_pages() to pin down the "page".
3. get_user_pages() calls flush_dcache_page(page) which ensures cache
   coherency between kernel and userspace mappings of "page".  However
   flush_dcache_page(page) may not invalidate I-Cache over this range
   for all cases, specifically, I-Cache is not invalidated for the VIPT
   non-aliasing case.  So memory is consistent between kernel and user
   space mappings of "page" but I-Cache may still be hot over this
   range.  IOW, we don't have to worry about flush_cache_page() before
   memcpy().
4. Now, for the copy_to_user_page() case, after memcpy(), we must flush
   the caches so memory is consistent with kernel cache entries and
   invalidate the I-Cache if this mm region is executable.  We don't
   need to do anything after memcpy() for the copy_from_user_page()
   case since kernel cache entries will be invalidated via the same
   process above if we access "page" again.  The flush_ptrace_access()
   function (borrowed from SPARC64 implementation) is added to handle
   cache flushing after memcpy() for the copy_to_user_page() case.

Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-02 18:43:20 +01:00
Lennert Buytenhek 260e98edc8 [ARM] 3761/1: fix armv4t breakage after adding thumb interworking to userspace helpers
Patch from Lennert Buytenhek

On armv4t systems, we have always compiled the kernel with -march=armv4
instead of -march=armv4t, which means that any use of bx will bomb out.

Commit ba9b5d7637 introduced the use of
bx in the kernel, which means we need to compile with -march=armv4t on
armv4t systems now.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-08-28 12:51:20 +01:00
Catalin Marinas ceaccbd2a6 [ARM] 3734/1: Fix the unused variable warning in __iounmap()
Patch from Catalin Marinas

This patch adds #ifdef around some variables in the arch/arm/mm/ioremap.c
file.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-29 08:29:30 +01:00
George G. Davis 7b1df1985c [ARM] 3737/1: Export ARM copy/clear_user_page symbols
Patch from George G. Davis

As reported by various folks on the ARM Linux kernel mailing list,
the video-buf.ko driver has undefined references on all ARM machines
which use it as observed during `make modules`:

Warning: "v4wb_clear_user_page" [drivers/media/video/video-buf.ko] undefined!

Similar warnings exist for all ARM machines which use this driver.
So this change adds the missing EXPORT_SYMBOLs to allow using this
driver as a module.

Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-29 08:29:27 +01:00
Lennert Buytenhek a6a38a6622 [ARM] 3736/1: xscale: don't mis-report 80219 as an iop32x
Patch from Lennert Buytenhek

The IOP 80219 xscale CPU is a stripped down version of the IOP32x.
But the fact that the 80219 and IOP32x are very similar doesn't mean
that they need to share a cpu table entry.  It's also somewhat confusing
for the end user to see the 80219 reported as an IOP32x, so this patch
splits the IOP32x cpu table entry to make a separate entry for the
80219.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-29 08:29:26 +01:00
Russell King 67f3a58856 [ARM] Fix warning in consistent.c
No need for 'cr' to be a local variable, which is unused in the
SMP case, and only used once in the UP case.  Just call get_cr()
directly.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-03 13:30:52 +01:00
Russell King 906243d07b [ARM] Fix bad asm instruction in proc-arm925.S
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-03 12:44:30 +01:00
Russell King 00eb0f6b65 [ARM] More missing proc-macros.S includes
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-03 12:36:07 +01:00
Lennert Buytenhek 7cddc39702 [ARM] 3708/2: fix SMP build after section ioremap changes
Patch from Lennert Buytenhek

Commit ff0daca525 broke the SMP build,
this patch fixes it up again.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-03 12:26:02 +01:00
Thomas Gleixner bb8d5a55a5 [PATCH] ARM: Fixup missing includes in arch/arm/mm/proc-<cputype>.S
For several proc-<cputype>.S files the include of proc-macros.S is
missing. Make it compile and work again.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-07-02 17:29:22 -07:00
Linus Torvalds a8c4c20dfa Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits)
  [ARM] 3541/2: workaround for PXA27x erratum E7
  [ARM] nommu: provide a way for correct control register value selection
  [ARM] 3705/1: add supersection support to ioremap()
  [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
  [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support
  [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency
  [ARM] 3703/1: Add help description for ARCH_EP80219
  [ARM] 3678/1: MMC: Make OMAP MMC work
  [ARM] 3677/1: OMAP: Update H2 defconfig
  [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1
  [ARM] Add section support to ioremap
  [ARM] Fix sa11x0 SDRAM selection
  [ARM] Set bit 4 on section mappings correctly depending on CPU
  [ARM] 3666/1: TRIZEPS4 [1/5] core
  ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring
  ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE
  ARM: OMAP: Update dmtimers
  ARM: OMAP: Make clock variables static
  ARM: OMAP: Fix GPMC compilation when DEBUG is defined
  ARM: OMAP: Mux updates for external DMA and GPIO
  ...
2006-07-02 15:04:12 -07:00
Nicolas Pitre 2dc7667b9d [ARM] 3541/2: workaround for PXA27x erratum E7
Patch from Nicolas Pitre

According to the Intel PXA27x Processor Family Specification
Update document (doc.nr. 280071-009) erratum E7, some care must be taken
to locate the disabling and re-enabling of the MMU to the beginning of a
cache line to avoid problems in some circumstances.

Credits to Simon Vogl <simon.vogl@researchstudios.at> for bringing this
up.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-01 21:29:32 +01:00
Russell King 3f8efdbe73 Merge nommu branch 2006-07-01 20:43:57 +01:00
Lennert Buytenhek a069c896d0 [ARM] 3705/1: add supersection support to ioremap()
Patch from Lennert Buytenhek

Analogous to the previous patch that allows ioremap() to use section
mappings, this patch allows ioremap() to use supersection mappings.
Original patch by Deepak Saxena.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-01 19:58:20 +01:00
Linus Torvalds 22a3e233ca Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial
* git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial:
  Remove obsolete #include <linux/config.h>
  remove obsolete swsusp_encrypt
  arch/arm26/Kconfig typos
  Documentation/IPMI typos
  Kconfig: Typos in net/sched/Kconfig
  v9fs: do not include linux/version.h
  Documentation/DocBook/mtdnand.tmpl: typo fixes
  typo fixes: specfic -> specific
  typo fixes in Documentation/networking/pktgen.txt
  typo fixes: occuring -> occurring
  typo fixes: infomation -> information
  typo fixes: disadvantadge -> disadvantage
  typo fixes: aquire -> acquire
  typo fixes: mecanism -> mechanism
  typo fixes: bandwith -> bandwidth
  fix a typo in the RTC_CLASS help text
  smb is no longer maintained

Manually merged trivial conflict in arch/um/kernel/vmlinux.lds.S
2006-06-30 15:39:30 -07:00