Commit Graph

10 Commits

Author SHA1 Message Date
Jie Zhang 41ba653f24 Blackfin: decouple unrelated cache settings to get exact behavior
The current cache options don't really represent the hardware features.
They end up setting different aspects of the hardware so that the end
result is to turn on/off the cache.  Unfortunately, when we hit cache
problems with the hardware, it's difficult to test different settings to
root cause the problem.  The current settings also don't cleanly allow for
different caching behaviors with different regions of memory.

So split the configure options such that they properly reflect the settings
that are applied to the hardware.

Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-06-22 21:15:59 -04:00
Sonic Zhang 47e9dedb72 Blackfin: add blackfin_invalidate_entire_icache for SMP systems
The KGDB code uses this when switching processors to make sure the icache
is in a valid state.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-06-13 07:20:07 -04:00
Jie Zhang 67834fa93d Blackfin: rename bfin_addr_dcachable to bfin_addr_dcacheable
The latter naming convention is much more common.

Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-06-13 07:20:06 -04:00
Mike Frysinger f339f46b05 Blackfin: fix detection of cached L2 SRAM
Make sure our bfin_addr_dcachable() function flags cached L2 SRAM properly
else memory easily goes unflushed when working with DMA.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-06-12 06:11:25 -04:00
Mike Frysinger 5d89137a17 Blackfin: fix data cache flushing when doing icache flushing
Make sure we flush all data caches and their write buffers before flushing
icache, otherwise random edge cases could crop up where stale data is read
into icache from external memory.  As fallout, punt the combined icache +
dcache flush function since we cannot safely do them back to back -- the
SSYNC is needed between the dcache flush and the icache flush.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2009-06-12 06:03:45 -04:00
Graf Yang 6b3087c64a Blackfin arch: SMP supporting patchset: Blackfin header files and machine common code
Blackfin dual core BF561 processor can support SMP like features.
https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like

In this patch, we provide SMP extend to Blackfin header files
and machine common code

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2009-01-07 23:14:39 +08:00
Mike Frysinger 8fb4f8f056 Blackfin arch: update cache flush prototypes with argument names to make them less mysterious
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-10-16 23:39:12 +08:00
Mike Frysinger 04be80ef0b Blackfin arch: move bfin_addr_dcachable() and friends into the cacheflush header where it belongs
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-10-16 23:33:53 +08:00
Mike Frysinger f4585a0847 Blackfin arch: only include asm/cplb.h when it is truly used
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-10-13 14:45:21 +08:00
Bryan Wu 639f657145 Blackfin arch: move include/asm-blackfin header files to arch/blackfin
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-08-27 10:51:02 +08:00