Commit Graph

6 Commits

Author SHA1 Message Date
Linus Walleij 40b37008eb gpio updates for v5.11-rc1
- several refactoring patches of the core gpiolib code
 - add support for NXP PCAL9554B/C to gpio-pca953x
 - allow probing mockup devices from device tree
 - refactoring and improvements to gpio-rcar
 - improvements to locking in gpio-tegra
 - code shrink in gpiolib devres
 - get the irq offset from device tree in gpio-sifive
 - major refactoring of gpio-exar
 - convert gpio-mvebu pwm access to regmap
 - create a new submenu for virtual GPIO drivers
 - fix clang fall-through warnings treewide
 - minor driver refactoring and tweaks sprinkled all over
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Merge tag 'gpio-updates-for-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel

gpio updates for v5.11-rc1

- several refactoring patches of the core gpiolib code
- add support for NXP PCAL9554B/C to gpio-pca953x
- allow probing mockup devices from device tree
- refactoring and improvements to gpio-rcar
- improvements to locking in gpio-tegra
- code shrink in gpiolib devres
- get the irq offset from device tree in gpio-sifive
- major refactoring of gpio-exar
- convert gpio-mvebu pwm access to regmap
- create a new submenu for virtual GPIO drivers
- fix clang fall-through warnings treewide
- minor driver refactoring and tweaks sprinkled all over
2020-12-09 15:17:24 +01:00
Linus Walleij 011a78c194 gpio: sifive: Set affinity callback to parent
This assigns the .irq_set_affinity to the parent callback.
I assume the sifive GPIO can be used in systems with
SMP.

I used the pattern making the hirerarchy tolerant for missing
parent as in Marc's earlier patches.

Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Yash Shah <yash.shah@sifive.com>
Cc: Wesley W. Terpstra <wesley@sifive.com>
Link: https://lore.kernel.org/r/20201117213351.249668-1-linus.walleij@linaro.org
2020-12-04 09:05:12 +01:00
Greentime Hu f52d6d8b43 gpio: sifive: To get gpio irq offset from device tree data
We can get hwirq number of the gpio by its irq_data->hwirq so that we don't
need to add more macros for different platforms. This patch is tested in
SiFive Unleashed board and SiFive Unmatched board.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2020-11-18 09:28:43 +01:00
Damien Le Moal b72de3ff19 gpio: sifive: Fix SiFive gpio probe
Fix the check on the number of IRQs to allow up to the maximum (32)
instead of only the maximum minus one.

Fixes: 96868dce64 ("gpio/sifive: Add GPIO driver for SiFive SoCs")
Cc: stable@vger.kernel.org
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Link: https://lore.kernel.org/r/20201107081420.60325-10-damien.lemoal@wdc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-11-11 09:53:09 +01:00
Yash Shah a924eae751 gpio: sifive: fix static checker warning
Typcasting "irq_state" leads to the below static checker warning:
The fix is to declare "irq_state" as unsigned long instead of u32.

	drivers/gpio/gpio-sifive.c:97 sifive_gpio_irq_enable()
	warn: passing casted pointer '&chip->irq_state' to
	'assign_bit()' 32 vs 64.

Fixes: 96868dce64 ("gpio/sifive: Add GPIO driver for SiFive SoCs")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Link: https://lore.kernel.org/r/1580189061-14091-1-git-send-email-yash.shah@sifive.com
Reviewed-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-02-10 13:54:17 +01:00
Yash Shah 96868dce64 gpio/sifive: Add GPIO driver for SiFive SoCs
Adds the GPIO driver for SiFive RISC-V SoCs.

Signed-off-by: Wesley W. Terpstra <wesley@sifive.com>
[Atish: Various fixes and code cleanup]
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/1575976274-13487-6-git-send-email-yash.shah@sifive.com
2020-01-20 19:10:03 +00:00