Commit Graph

77 Commits

Author SHA1 Message Date
Mika Westerberg c538b94367 pinctrl: intel: Only restore pins that are used by the driver
Dell XPS 13 (and maybe some others) uses a GPIO (CPU_GP_1) during suspend
to explicitly disable USB touchscreen interrupt. This is done to prevent
situation where the lid is closed the touchscreen is left functional.

The pinctrl driver (wrongly) assumes it owns all pins which are owned by
host and not locked down. It is perfectly fine for BIOS to use those pins
as it is also considered as host in this context.

What happens is that when the lid of Dell XPS 13 is closed, the BIOS
configures CPU_GP_1 low disabling the touchscreen interrupt. During resume
we restore all host owned pins to the known state which includes CPU_GP_1
and this overwrites what the BIOS has programmed there causing the
touchscreen to fail as no interrupts are reaching the CPU anymore.

Fix this by restoring only those pins we know are explicitly requested by
the kernel one way or other.

Cc: stable@vger.kernel.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=176361
Reported-by: AceLan Kao <acelan.kao@canonical.com>
Tested-by: AceLan Kao <acelan.kao@canonical.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-18 14:38:16 +02:00
Ville Syrjälä a171bc51fa pinctrl: baytrail: Fix lockdep
Initialize the spinlock before using it.

INFO: trying to register non-static key.
the code is fine but needs lockdep annotation.
turning off the locking correctness validator.
CPU: 2 PID: 1 Comm: swapper/0 Not tainted 4.8.0-dwc-bisect #4
Hardware name: Intel Corp. VALLEYVIEW C0 PLATFORM/BYT-T FFD8, BIOS BLAKFF81.X64.0088.R10.1403240443 FFD8_X64_R_2014_13_1_00 03/24/2014
 0000000000000000 ffff8800788ff770 ffffffff8133d597 0000000000000000
 0000000000000000 ffff8800788ff7e0 ffffffff810cfb9e 0000000000000002
 ffff8800788ff7d0 ffffffff8205b600 0000000000000002 ffff8800788ff7f0
Call Trace:
 [<ffffffff8133d597>] dump_stack+0x67/0x90
 [<ffffffff810cfb9e>] register_lock_class+0x52e/0x540
 [<ffffffff810d2081>] __lock_acquire+0x81/0x16b0
 [<ffffffff810cede1>] ? save_trace+0x41/0xd0
 [<ffffffff810d33b2>] ? __lock_acquire+0x13b2/0x16b0
 [<ffffffff810cf05a>] ? __lock_is_held+0x4a/0x70
 [<ffffffff810d3b1a>] lock_acquire+0xba/0x220
 [<ffffffff8136f1fe>] ? byt_gpio_get_direction+0x3e/0x80
 [<ffffffff81631567>] _raw_spin_lock_irqsave+0x47/0x60
 [<ffffffff8136f1fe>] ? byt_gpio_get_direction+0x3e/0x80
 [<ffffffff8136f1fe>] byt_gpio_get_direction+0x3e/0x80
 [<ffffffff813740a9>] gpiochip_add_data+0x319/0x7d0
 [<ffffffff81631723>] ? _raw_spin_unlock_irqrestore+0x43/0x70
 [<ffffffff8136fe3b>] byt_pinctrl_probe+0x2fb/0x620
 [<ffffffff8142fb0c>] platform_drv_probe+0x3c/0xa0
...

Based on the diff it looks like the problem was introduced in
commit 71e6ca61e8 ("pinctrl: baytrail: Register pin control handling")
but I wasn't able to verify that empirically as the parent commit
just oopsed when I tried to boot it.

Cc: Cristina Ciocan <cristina.ciocan@intel.com>
Cc: stable@vger.kernel.org
Fixes: 71e6ca61e8 ("pinctrl: baytrail: Register pin control handling")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-18 14:36:13 +02:00
Linus Walleij 8d0a0ac0ab Merge branch 'fixes' into devel 2016-09-23 17:41:40 +02:00
Nilesh Bacchewar 01dabe91b1 pinctrl: intel: Configure GPIO chip IRQ as wakeup interrupts
On some Intel BXT platform, wake-up from suspend-to-idle on pressing
power-button is not working. Its noticed that gpio-keys driver marking the
second level IRQ/power-button as wake capable but Intel pintctrl
driver is missing to mark GPIO chip/controller IRQ which first level IRQ
as wake cable if its GPIO pin IRQ is wakeble. So, though the first level
IRQ gets generated on power-button press, since it is not marked as
wake capable resume/wake-up flow is not happening.
Intel pintctrl/GPIO driver need to mark GPIO chip/controller IRQ (first
level IRQ) as wake capable iff GPIO pin's IRQ (second level IRQ) is marked
as wake cable.

Changes in v2:
 - Add missing irq initialisation.

Signed-off-by: Nilesh Bacchewar <nilesh.bacchewar@intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 15:14:21 +02:00
Mika Westerberg d1073418d9 pinctrl: cherryview: Convert to use devm_gpiochip_add_data()
This simplifies the error handling and allows us to drop the whole
chv_pinctrl_remove() function.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 14:59:42 +02:00
Mika Westerberg 47c950d102 pinctrl: cherryview: Do not add all southwest and north GPIOs to IRQ domain
It turns out that for north and southwest communities, they can only
generate GPIO interrupts for lower 8 interrupts (IntSel value). The upper
part (8-15) can only generate GPEs (General Purpose Events).

Now the reason why EC events such as pressing hotkeys does not work if we
mask all the interrupts is that in order to generate either interrupts or
GPEs the INTMASK register must have that particular interrupt unmasked. In
case of GPEs the CPU does not trigger normal interrupt (and thus the GPIO
driver does not see it) but instead it causes SCI (System Control
Interrupt) to be triggered with the GPE in question set.

To make this all work as expected we only add those GPIOs to the IRQ domain
that can actually generate interrupts (IntSel value 0-7) and skip others.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 14:57:33 +02:00
Vincent Stehlé c11a0442b0 pinctrl: intel: merrifield: fix dup size in probe
In function mrfld_pinctrl_probe(), when duplicating the mrfld_families
array the requested memory region length is multiplied once too many by the
number of elements in the original array. Fix this to spare some memory.

Fixes: 4e80c8f505 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Signed-off-by: Vincent Stehlé <vincent.stehle@intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-12 15:45:16 +02:00
Mika Westerberg bcb48cca23 pinctrl: cherryview: Do not mask all interrupts in probe
The Cherryview GPIO controller has 8 or 16 wires connected to the I/O-APIC
which can be used directly by the platform/BIOS or drivers. One such wire
is used as SCI (System Control Interrupt) which ACPI depends on to be able
to trigger GPEs (General Purpose Events).

The pinctrl driver itself uses another IRQ resource which is wire OR of all
the 8 (or 16) wires and follows what BIOS has programmed to the IntSel
register of each pin.

Currently the driver masks all interrupts at probe time and this prevents
these direct interrupts from working as expected. The reason for this is
that some early stage prototypes had some pins misconfigured causing lots
of spurious interrupts.

We fix this by leaving the interrupt mask untouched. This allows SCI and
other direct interrupts work properly. What comes to the possible spurious
interrupts we switch the default handler to be handle_bad_irq() instead of
handle_simple_irq() (which was not correct anyway).

Reported-by: Yu C Chen <yu.c.chen@intel.com>
Reported-by: Anisse Astier <anisse@astier.eu>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-22 15:57:04 +02:00
Andy Shevchenko e95d0dfb22 pinctrl: intel: merrifield: Add missed header
On x86 builds the absense of <linux/io.h> makes static analyzer and compiler
unhappy which fails to build the driver.

CHECK   drivers/pinctrl/intel/pinctrl-merrifield.c
drivers/pinctrl/intel/pinctrl-merrifield.c:518:17:
  error: undefined identifier 'readl'
drivers/pinctrl/intel/pinctrl-merrifield.c:570:17:
  error: undefined identifier 'readl'
drivers/pinctrl/intel/pinctrl-merrifield.c:575:9:
  error: undefined identifier 'writel'
drivers/pinctrl/intel/pinctrl-merrifield.c:645:17:
  error: undefined identifier 'readl'
  CC      drivers/pinctrl/intel/pinctrl-merrifield.o
drivers/pinctrl/intel/pinctrl-merrifield.c: In function ‘mrfld_pin_dbg_show’:
drivers/pinctrl/intel/pinctrl-merrifield.c:518:10:
  error: implicit declaration of function ‘readl’
  [-Werror=implicit-function-declaration]
  value = readl(bufcfg);
            ^
drivers/pinctrl/intel/pinctrl-merrifield.c: In function ‘mrfld_update_bufcfg’:
drivers/pinctrl/intel/pinctrl-merrifield.c:575:2:
  error: implicit declaration of function ‘writel’
  [-Werror=implicit-function-declaration]
  writel(value, bufcfg);
    ^
cc1: some warnings being treated as errors

Add header to the top of the module.

Fixes: 4e80c8f505 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-10 15:46:28 +02:00
Linus Torvalds d94ba9e7d8 This is the bulk of pin control changes for the v4.8 kernel cycle.
New drivers:
 
 - New driver for Oxnas pin control and GPIO. This ARM-based chipset
   is used in a few storage (NAS) type devices.
 
 - New driver for the MAX77620/MAX20024 pin controller portions.
 
 - New driver for the Intel Merrifield pin controller.
 
 New subdrivers:
 
 - New subdriver for the Qualcomm MDM9615
 
 - New subdriver for the STM32F746 MCU
 
 - New subdriver for the Broadcom NSP SoC.
 
 Cleanups:
 
 - Demodularization of bool compiled-in drivers.
 
 Apart from this there is just regular incremental improvements to
 a lot of drivers, especially Uniphier and PFC.
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Merge tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.8 kernel cycle.

  Nothing stands out as especially exiting: new drivers, new subdrivers,
  lots of cleanups and incremental features.

  Business as usual.

  New drivers:

   - New driver for Oxnas pin control and GPIO.  This ARM-based chipset
     is used in a few storage (NAS) type devices.

   - New driver for the MAX77620/MAX20024 pin controller portions.

   - New driver for the Intel Merrifield pin controller.

  New subdrivers:

   - New subdriver for the Qualcomm MDM9615

   - New subdriver for the STM32F746 MCU

   - New subdriver for the Broadcom NSP SoC.

  Cleanups:

   - Demodularization of bool compiled-in drivers.

  Apart from this there is just regular incremental improvements to a
  lot of drivers, especially Uniphier and PFC"

* tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (131 commits)
  pinctrl: fix pincontrol definition for marvell
  pinctrl: xway: fix typo
  Revert "pinctrl: amd: make it explicitly non-modular"
  pinctrl: iproc: Add NSP and Stingray GPIO support
  pinctrl: Update iProc GPIO DT bindings
  pinctrl: bcm: add OF dependencies
  pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe()
  pinctrl: Add STM32F746 MCU support
  pinctrl: intel: Protect set wake flow by spin lock
  pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe()
  pinctrl: uniphier: add Ethernet pin-mux settings
  sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the code
  pinctrl: ns2: fix return value check in ns2_pinmux_probe()
  pinctrl: qcom: update DT bindings with ebi2 groups
  pinctrl: qcom: establish proper EBI2 pin groups
  pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macro
  Documentation: dt: Add new compatible to STM32 pinctrl driver bindings
  includes: dt-bindings: Add STM32F746 pinctrl DT bindings
  pinctrl: sunxi: fix nand0 function name for sun8i
  pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11
  ...
2016-07-28 17:06:51 -07:00
Andy Shevchenko 9a520fd99f pinctrl: intel: Protect set wake flow by spin lock
It seems intel_gpio_irq_wake() misses lock protection against I/O flow.
Use spin lock here as well.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-07-11 11:15:33 +02:00
Andy Shevchenko 4e80c8f505 pinctrl: intel: Add Intel Merrifield pin controller support
This driver adds pinctrl support for Intel Merrifield. The IP block which is
called Family-Level Interface Shim is a separate entity in SoC. The GPIO driver
(gpio-intel-mid.c) will be updated accordingly to support pinctrl interface.

Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-29 09:59:35 +02:00
Cristina Ciocan b41aa4f847 pinctrl: baytrail: Fix mingled clock pins
Fix plt clock 3, 4 and 5 pins, which were not in the proper order.

Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-23 11:05:04 +02:00
Mika Westerberg 1a7d1cb81e pinctrl: intel: Prevent force threading of the interrupt handler
The pinctrl-intel needs to use request_irq() instead of chained interrupt
handling because it shares the interrupt with multiple GPIO host
controllers found on Intel CPUs. In -rt all such interrupts are forced to
run in thread context which triggers following warning:

 WARNING: CPU: 0 PID: 530 at kernel/irq/handle.c:151 handle_irq_event_percpu+0x23d/0x240
 irq 348 handler irq_default_primary_handler+0x0/0x10 enabled interrupts
 Modules linked in:
 CPU: 0 PID: 530 Comm: irq/14-INT3452: Not tainted 4.6.2-rt5 #1060
  0000000000000000 ffff88007a257c98 ffffffff812d8494 ffff88007a257ce8
  0000000000000000 ffff88007a257cd8 ffffffff8105e554 000000977a257d90
  ffff88007a37a380 000000000000015c 0000000000000002 0000000000000000
 Call Trace:
  [<ffffffff812d8494>] dump_stack+0x4f/0x6b
  [<ffffffff8105e554>] __warn+0xe4/0x100
  [<ffffffff8105e5bf>] warn_slowpath_fmt+0x4f/0x60
  [<ffffffff810b18f0>] ? __synchronize_hardirq+0x60/0x60
  [<ffffffff810b17fd>] handle_irq_event_percpu+0x23d/0x240
  [<ffffffff810b1862>] handle_irq_event+0x62/0x90
  [<ffffffff810b4e1f>] handle_edge_irq+0x8f/0x190
  [<ffffffff810b0d82>] generic_handle_irq+0x22/0x30
  [<ffffffff81307abc>] intel_gpio_irq+0xdc/0x150
  [<ffffffff810b2293>] irq_forced_thread_fn+0x23/0x70
  [<ffffffff810b250b>] irq_thread+0x13b/0x1d0
  [<ffffffff8167b844>] ? __schedule+0x2e4/0x5a0
  [<ffffffff810b2270>] ? irq_finalize_oneshot.part.37+0xd0/0xd0
  [<ffffffff810b25a0>] ? irq_thread+0x1d0/0x1d0
  [<ffffffff810b23d0>] ? wake_threads_waitq+0x30/0x30
  [<ffffffff8107e624>] kthread+0xd4/0xf0
  [<ffffffff8167ec27>] ? _raw_spin_unlock_irq+0x17/0x40
  [<ffffffff8167f592>] ret_from_fork+0x22/0x40
  [<ffffffff8107e550>] ? kthread_worker_fn+0x190/0x190

The handle_irq_event_* functions (and I suppose generic_handle_irq()) is
expected to be called with interrupts disabled and they rightfully complain
here because we run in thread context with interrupts enabled.

Fix this by adding IRQF_NO_THREAD flag when the master interrupt is
requested. This prevents forced threading of the interrupt used by the GPIO
host controllers.

Reported-by: Kim Tatt Chuah <kim.tatt.chuah@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-18 10:35:47 +02:00
Mika Westerberg 27d9098cff pinctrl: intel: Use raw_spinlock for locking
When running -rt kernel and GPIO interrupt happens we get following

 BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:931
 in_atomic(): 1, irqs_disabled(): 0, pid: 530, name: irq/14-INT3452:
 Preemption disabled at:[<ffffffff810b4dab>] handle_edge_irq+0x1b/0x190

 CPU: 0 PID: 530 Comm: irq/14-INT3452: Not tainted 4.6.2-rt5 #1060
  0000000000000000 ffff88007a257d58 ffffffff812d8494 0000000000000000
  ffff88017a330000 ffff88007a257d78 ffffffff81083a11 ffff88007a252430
  ffff88007a252430 ffff88007a257d90 ffffffff8167ef20 000000000000001a
 Call Trace:
  [<ffffffff812d8494>] dump_stack+0x4f/0x6b
  [<ffffffff81083a11>] ___might_sleep+0xe1/0x160
  [<ffffffff8167ef20>] rt_spin_lock+0x20/0x50
  [<ffffffff81308c6d>] intel_gpio_irq_ack+0x2d/0x80
  [<ffffffff810b4e0b>] handle_edge_irq+0x7b/0x190
  [<ffffffff810b0d82>] generic_handle_irq+0x22/0x30
  [<ffffffff81307abc>] intel_gpio_irq+0xdc/0x150
  [<ffffffff810b2293>] irq_forced_thread_fn+0x23/0x70
  [<ffffffff810b250b>] irq_thread+0x13b/0x1d0
  [<ffffffff8167b844>] ? __schedule+0x2e4/0x5a0
  [<ffffffff810b2270>] ? irq_finalize_oneshot.part.37+0xd0/0xd0
  [<ffffffff810b25a0>] ? irq_thread+0x1d0/0x1d0
  [<ffffffff810b23d0>] ? wake_threads_waitq+0x30/0x30
  [<ffffffff8107e624>] kthread+0xd4/0xf0
  [<ffffffff8167ec27>] ? _raw_spin_unlock_irq+0x17/0x40
  [<ffffffff8167f592>] ret_from_fork+0x22/0x40
  [<ffffffff8107e550>] ? kthread_worker_fn+0x190/0x190

The reason why this happens is because intel_gpio_irq_ack() is called with
desc->lock raw_spinlock locked which cannot sleep but our normal spinlock
(which is converted to rtmutex in -rt) is allowed to sleep. This causes
might_sleep() to trigger.

Fix this by converting the normal spinlock to a raw_spinlock.

Reported-by: Kim Tatt Chuah <kim.tatt.chuah@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-18 10:35:44 +02:00
Tan Jui Nee 0c3013bbe1 pinctrl/broxton: enable platform device in the absence of ACPI enumeration
This is to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind
with the Apollo Lake Pinctrl GPIO platform driver.

Signed-off-by: Tan Jui Nee <jui.nee.tan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-15 08:37:42 +02:00
Dan O'Donovan 77401d7fdf pinctrl: cherryview: add handlers for pin_config_group_get/set
Pin config get/set handlers for pin groups were previously not
implemented by this driver.  The pin_config_group_set is
particularly useful for applying a common config setting to all
pins in a specified group with a single call, without the caller
needing to reference each individual pin by name.

Signed-off-by: Dan O'Donovan <dan@emutex.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-15 08:37:40 +02:00
Dan O'Donovan ccdf81d08d pinctrl: cherryview: add option to set open-drain pin config
On some CHV platforms, we need an option to configure the
open-drain setting for these pins.  This adds support for the
PIN_CONFIG_DRIVE_PUSH_PULL and PIN_CONFIG_DRIVE_OPEN_DRAIN to
disable/enable open-drain mode for a specific pin.

Signed-off-by: Dan O'Donovan <dan@emutex.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-15 08:37:39 +02:00
Dan O'Donovan 0bd50d719b pinctrl: cherryview: prevent concurrent access to GPIO controllers
Due to a silicon issue on the Atom X5-Z8000 "Cherry Trail" processor
series, a common lock must be used to prevent concurrent accesses
across the 4 GPIO controllers managed by this driver.

See Intel Atom Z8000 Processor Series Specification Update
(Rev. 005), errata #CHT34, for further information.

Cc: stable <stable@vger.kernel.org>
Signed-off-by: Dan O'Donovan <dan@emutex.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-15 08:37:39 +02:00
Paul Gortmaker 360943a8d2 pinctrl: baytrail: make it explicitly non-modular
The Kconfig currently controlling compilation of this code is:

config PINCTRL_BAYTRAIL
        bool "Intel Baytrail GPIO pin control"

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

We explicitly disallow a driver unbind, since that doesn't have a
sensible use case anyway, and it allows us to drop the ".remove"
code for non-modular drivers.

Since module_init() was already not in use in this driver, we don't
have any concerns with init ordering changes here.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.

Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-13 08:25:56 +02:00
Andrew Morton bbccb9c7bb drivers/pinctrl/intel/pinctrl-baytrail.c: fix build with gcc-4.4
gcc-4.4 and thereabouts has issues with initializers of anonymous
unions, and it generates the following warnings:

  drivers/pinctrl/intel/pinctrl-baytrail.c:413: error: unknown field 'simple_funcs' specified in initializer
  drivers/pinctrl/intel/pinctrl-baytrail.c:413: warning: missing braces around initializer
  drivers/pinctrl/intel/pinctrl-baytrail.c:413: warning: (near initialization for 'byt_score_groups[0].<anonymous>')
  drivers/pinctrl/intel/pinctrl-baytrail.c:415: error: unknown field 'simple_funcs' specified in initializer
  drivers/pinctrl/intel/pinctrl-baytrail.c:417: error: unknown field 'simple_funcs' specified in initializer
  ...

Work around this.

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-05-26 15:35:44 -07:00
Linus Torvalds a37571a29e Pin control bulk changes for the v4.7 kernel cycle:
Core changes:
 
 - Add the devm_pinctrl_register() API and switch all applicable drivers
   to use it, saving lots of lines of code all over the place.
 
 New drivers:
 
 - New driver for the Broadcom NS2 SoC.
 
 - New subdriver for the PXA25x SoCs.
 
 - New subdriver for the AMLogic Meson GXBB SoC.
 
 Driver improvements:
 
 - The Intel Baytrail driver now properly supports pin control.
 
 - The Nomadik, Rockchip, Broadcom BCM2835 supports the .get_direction() callback in
   the GPIO portions.
 
 - Continued development and stabilization of several SH-PFC
   SoC subdrivers: r8a7795, r8a7790, r8a7794 etc.
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Merge tag 'pinctrl-v4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This kernel cycle was quite calm when it comes to pin control and
  there is really just one major change, and that is the introduction of
  devm_pinctrl_register() managed resources.

  Apart from that linear development, details below.

  Core changes:

   - Add the devm_pinctrl_register() API and switch all applicable
     drivers to use it, saving lots of lines of code all over the place.

  New drivers:

   - driver for the Broadcom NS2 SoC

   - subdriver for the PXA25x SoCs

   - subdriver for the AMLogic Meson GXBB SoC

  Driver improvements:

   - the Intel Baytrail driver now properly supports pin control

   - Nomadik, Rockchip, Broadcom BCM2835 support the .get_direction()
     callback in the GPIO portions

   - continued development and stabilization of several SH-PFC SoC
     subdrivers: r8a7795, r8a7790, r8a7794 etc"

* tag 'pinctrl-v4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (85 commits)
  Revert "pinctrl: tegra: avoid parked_reg and parked_bank"
  pinctrl: meson: Fix eth_tx_en bit index
  pinctrl: tegra: avoid parked_reg and parked_bank
  pinctrl: tegra: Correctly check the supported configuration
  pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC
  pinctrl: rockchip: fix pull setting error for rk3399
  pinctrl: stm32: Implement .pin_config_dbg_show()
  pinctrl: nomadik: hide nmk_gpio_get_mode when unused
  pinctrl: ns2: rename pinctrl_utils_dt_free_map
  pinctrl: at91: Merge clk_prepare and clk_enable into clk_prepare_enable
  pinctrl: at91: Make at91_gpio_template const
  pinctrl: baytrail: fix some error handling in debugfs
  pinctrl: ns2: add pinmux driver support for Broadcom NS2 SoC
  pinctrl: sirf/atlas7: trivial fix of spelling mistake on flagged
  pinctrl: sh-pfc: Kill unused variable in sh_pfc_remove()
  pinctrl: nomadik: implement .get_direction()
  pinctrl: nomadik: use BIT() with offsets consequently
  pinctrl: exynos5440: Use off-stack memory for pinctrl_gpio_range
  pinctrl: zynq: Use devm_pinctrl_register() for pinctrl registration
  pinctrl: u300: Use devm_pinctrl_register() for pinctrl registration
  ...
2016-05-19 12:50:56 -07:00
Dan Carpenter 22bbd21b81 pinctrl: baytrail: fix some error handling in debugfs
We need to unlock before continuing.  Also the continue was accidentally
left out on one error path which would lead to a NULL dereference.

Fixes: 86e3ef812f ('pinctrl: baytrail: Update gpio chip operations')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-04-30 13:34:53 +02:00
Laxman Dewangan 54d46cd7d2 pinctrl: intel: Use devm_pinctrl_register() for pinctrl registration
Use devm_pinctrl_register() for pin control registration and clean
error path.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-04-21 00:02:28 +02:00
Laxman Dewangan 7cf061fadd pinctrl: cherryview: Use devm_pinctrl_register() for pinctrl registration
Use devm_pinctrl_register() for pin control registration and clean
error path.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-04-21 00:02:24 +02:00
Cristina Ciocan 658b476c74 pinctrl: baytrail: Add debounce configuration
Make debounce setting and getting functionality available when
configurating a certain pin.

Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-04-04 16:14:28 +02:00
Cristina Ciocan 71e6ca61e8 pinctrl: baytrail: Register pin control handling
This patch updates device's probing, removal and irq handling in order to
register it as pinctrl device. Pin control data is matched by ACPI UID,
since it is passed along as driver data in acpi_device_id structure.

Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-04-04 16:12:07 +02:00
Cristina Ciocan 9f573b98ca pinctrl: baytrail: Update irq chip operations
This patch updates the irq chip implementation in order
to interact with the pin control chip model: the chip
contains reference to SOC data and pin/group/community
information is retrieved through the SOC reference.

Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-04-04 16:09:40 +02:00
Cristina Ciocan 86e3ef812f pinctrl: baytrail: Update gpio chip operations
This patch updates the gpio chip implementation in order
to interact with the pin control model: the chip contains
reference to SOC data and pin/group/community information
is retrieved through the SOC reference.

Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-04-04 16:02:19 +02:00
Cristina Ciocan c501d0b149 pinctrl: baytrail: Add pin control operations
Add implementation for:
- pin control, group information retrieval: count, name and pins
- pin muxing:
  - function information (count, name and groups)
  - mux setting
  - gpio control (enable, disable, set direction)
- pin configuration:
  - pull disable
  - pull up/down and pull strength
  - debounce
  - any other option is treated as not supported.

Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-04-04 15:58:28 +02:00
Cristina Ciocan c8f5c4c7c8 pinctrl: baytrail: Add pin control data structures
In order to implement pin control for Baytrail, we need data
structures in which to store and pass along pin, group, function,
community and SOC data information.

Baytrail has 3 GPIO controllers. Add SCORE, NCORE and SUS
controller data:
- pins (for all controllers),
- pad map for pins (for all controllers; we need this since pads
  are not ordered),
- groups (for SCORE and SUS controllers),
- functions (for SCORE and SUS controllers),
- communities (for all controllers),
- soc specific data gathering all of the above and the ACPI UID
  (for all controllers)

This information is useful for pin control functionality.
NCORE data is lighter than the other two controllers' due to
lack of pin documentation in the public datasheet.

Datasheet:
http://www.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e3800-family-datasheet.html

Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-04-04 15:55:21 +02:00
Qi Zheng a939bb57cd pinctrl: intel: implement gpio_irq_enable
There is unexpected gpio interrupt after irq_enable. If not
implemeted gpio_irq_enable callback, irq_enable calls irq_unmask
instead. But if there was interrupt set before the irq_enable,
unmask it may trigger the unexpected interrupt. By implementing
the gpio_irq_enable callback, do interrupt status ack, the issue
has gone.

Signed-off-by: Qi Zheng <qi.zheng@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Qipeng Zha <qipeng.zha@intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-03-30 10:57:52 +02:00
Qipeng Zha bf380cfa60 pinctrl: intel: make the high level interrupt working
High level trigger mode of GPIO interrupt is not set correctly
in intel_gpio_irq_type(), and will make this kind of interrupt
not respond.

Signed-off-by: Qi Zheng <qi.zheng@intel.com>
Signed-off-by: Qipeng Zha <qipeng.zha@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-03-30 10:57:52 +02:00
Jean Delvare 2f749c3ac7 pinctrl: intel: Remove unneeded header includes
pinctrl-intel doesn't use anything from <linux/init.h>,
<linux/acpi.h>, <linux/gpio.h> or <linux/pm.h>, so it should not
include these header files.

Signed-off-by: Jean Delvare <jdelvare@suse.de>
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-12 13:56:57 +01:00
Linus Walleij acfd4c633a pinctrl: intel: use gpiochip data pointer
This makes the driver use the data pointer added to the gpio_chip
to store a pointer to the state container instead of relying on
container_of().

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-05 14:14:49 +01:00
Linus Walleij 0587d3db00 pinctrl: cherryview: use gpiochip data pointer
This makes the driver use the data pointer added to the gpio_chip
to store a pointer to the state container instead of relying on
container_of().

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-05 14:14:48 +01:00
Linus Walleij bf9a5c96c8 pinctrl: baytrail: use gpiochip data pointer
This makes the driver use the data pointer added to the gpio_chip
to store a pointer to the state container instead of relying on
container_of().

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-05 14:14:47 +01:00
Linus Walleij 3bde87714e pinctrl: baytrail: Be sure to clamp return value
As we want gpio_chip .get() calls to be able to return negative
error codes and propagate to drivers, we need to go over all
drivers and make sure their return values are clamped to [0,1].
We do this by using the ret = !!(val) design pattern.

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-26 22:28:33 +01:00
Linus Walleij 0529357f10 Linux 4.4-rc6
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Merge tag 'v4.4-rc6' into devel

Linux 4.4-rc6
2015-12-21 09:36:21 +01:00
Qipeng Zha 99a735b3c2 pinctrl: intel: fix offset calculation issue of register PAD_OWN
The calculation equation of PAD_OWN register offset is not
correct for Broxton, verified this fix will get right
offset for Broxton.

Signed-off-by: Qi Zheng <qi.zheng@intel.com>
Signed-off-by: Qipeng Zha <qipeng.zha@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10 23:01:42 +01:00
Qipeng Zha 618a919b4c pinctrl: intel: fix bug of register offset calculation
The group size for registers PADCFGLOCK, HOSTSW_OWN, GPI_IS,
GPI_IE, are not 24 for Broxton, Add a parameter to allow
different platform to set correct value.

Signed-off-by: Qi Zheng <qi.zheng@intel.com>
Signed-off-by: Qipeng Zha <qipeng.zha@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10 23:01:41 +01:00
Linus Walleij 58383c7842 gpio: change member .dev to .parent
The name .dev in a struct is normally reserved for a struct device
that is let us say a superclass to the thing described by the struct.
struct gpio_chip stands out by confusingly using a struct device *dev
to point to the parent device (such as a platform_device) that
represents the hardware. As we want to give gpio_chip:s real devices,
this is not working. We need to rename this member to parent.

This was done by two coccinelle scripts, I guess it is possible to
combine them into one, but I don't know such stuff. They look like
this:

@@
struct gpio_chip *var;
@@
-var->dev
+var->parent

and:

@@
struct gpio_chip var;
@@
-var.dev
+var.parent

and:

@@
struct bgpio_chip *var;
@@
-var->gc.dev
+var->gc.parent

Plus a few instances of bgpio that I couldn't figure out how
to teach Coccinelle to rewrite.

This patch hits all over the place, but I *strongly* prefer this
solution to any piecemal approaches that just exercise patch
mechanics all over the place. It mainly hits drivers/gpio and
drivers/pinctrl which is my own backyard anyway.

Cc: Haavard Skinnemoen <hskinnemoen@gmail.com>
Cc: Rafał Miłecki <zajec5@gmail.com>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Cc: Alek Du <alek.du@intel.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Takashi Iwai <tiwai@suse.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Jiri Kosina <jkosina@suse.cz>
Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
Acked-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-11-19 09:24:35 +01:00
Linus Torvalds e86328c489 This is the bulk of GPIO changes for v4.4:
GPIO core:
 - Define and handle flags for open drain/open collector
   and open source/open emitter, also know as "single-ended"
   configurations.
 - Generic request/free operations that handle calling out
   to the (optional) pin control backend.
 - Some refactoring related to an ABI change that did not
   happen, yet provide useful.
 - Added a real-time compliance checklist. Many GPIO chips
   have irqchips, and need to think this over with the RT
   patches going upstream.
 - Restructure, fix and clean up Kconfig menus a bit.
 
 New drivers:
 - New driver for AMD Promony.
 - New driver for ACCES 104-IDIO-16, a port-mapped I/O
   card, ISA-style. Very retro.
 
 Subdriver changes:
 - OMAP changes to handle real time requirements.
 - Handle trigger types for edge and level IRQs on PL061
   properly. As this hardware is very common it needs to
   set a proper example for others to follow.
 - Some container_of() cleanups.
 - Delete the unused MSM driver in favor of the driver that
   is embedded inside the pin control driver.
 - Cleanup of the ath79 GPIO driver used by many, many
   OpenWRT router targets.
 - A consolidated IT87xx driver replacing the earlier
   very specific IT8761e driver.
 - Handle the TI TCA9539 in the PCA953x driver. Also
   handle ACPI devices in this subdriver.
 - Drop xilinx arch dependencies as these FPGAs seem to
   profilate over a few different architectures. MIPS and
   ARM come to mind.
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Merge tag 'gpio-v4.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO updates from Linus Walleij:
 "Here is the bulk of GPIO changes for the v4.4 development cycle.

  The only changes hitting outside drivers/gpio are in the pin control
  subsystem and these seem to have settled nicely in linux-next.

  Development mistakes and catfights are nicely documented in the
  reverts as you can see.  The outcome of the ABI fight is that we're
  working on a chardev ABI for GPIO now, where hope to show results for
  the v4.5 kernel.

  Summary of changes:

  GPIO core:
   - Define and handle flags for open drain/open collector and open
     source/open emitter, also know as "single-ended" configurations.
   - Generic request/free operations that handle calling out to the
     (optional) pin control backend.
   - Some refactoring related to an ABI change that did not happen, yet
     provide useful.
   - Added a real-time compliance checklist.  Many GPIO chips have
     irqchips, and need to think this over with the RT patches going
     upstream.
   - Restructure, fix and clean up Kconfig menus a bit.

  New drivers:
   - New driver for AMD Promony.
   - New driver for ACCES 104-IDIO-16, a port-mapped I/O card,
     ISA-style.  Very retro.

  Subdriver changes:
   - OMAP changes to handle real time requirements.
   - Handle trigger types for edge and level IRQs on PL061 properly.  As
     this hardware is very common it needs to set a proper example for
     others to follow.
   - Some container_of() cleanups.
   - Delete the unused MSM driver in favor of the driver that is
     embedded inside the pin control driver.
   - Cleanup of the ath79 GPIO driver used by many, many OpenWRT router
     targets.
   - A consolidated IT87xx driver replacing the earlier very specific
     IT8761e driver.
   - Handle the TI TCA9539 in the PCA953x driver.  Also handle ACPI
     devices in this subdriver.
   - Drop xilinx arch dependencies as these FPGAs seem to profilate over
     a few different architectures.  MIPS and ARM come to mind"

* tag 'gpio-v4.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (57 commits)
  gpio: fix up SPI submenu
  gpio: drop surplus I2C dependencies
  gpio: drop surplus X86 dependencies
  gpio: dt-bindings: document the official use of "ngpios"
  gpio: MAINTAINERS: Add an entry for the ATH79 GPIO driver
  gpio / ACPI: Allow shared GPIO event to be read via operation region
  gpio: group port-mapped I/O drivers in a menu
  gpio: Add ACCES 104-IDIO-16 driver maintainer entry
  gpio: zynq: Document interrupt-controller DT binding
  gpio: xilinx: Drop architecture dependencies
  gpio: generic: Revert to old error handling in bgpio_map
  gpio: add a real time compliance notes
  Revert "gpio: add a real time compliance checklist"
  gpio: Add GPIO support for the ACCES 104-IDIO-16
  gpio: driver for AMD Promontory
  gpio: xlp: Convert to use gpiolib irqchip helpers
  gpio: add a real time compliance checklist
  gpio/xilinx: enable for MIPS
  gpiolib: Add and use OF_GPIO_SINGLE_ENDED flag
  gpiolib: Split GPIO flags parsing and GPIO configuration
  ...
2015-11-02 12:59:12 -08:00
Mika Westerberg ee1a6ca43d pinctrl: intel: Add Intel Broxton pin controller support
This driver adds pinctrl/GPIO support for Intel Broxton. The GPIO
controller is based on the same hardware design that is already used in
Intel Sunrisepoint so we leverage the core driver here.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-27 13:32:13 +01:00
Mika Westerberg 4341e8a545 pinctrl: intel: Allow requesting pins which are in ACPI mode as GPIOs
Reserved for ACPI actually means that in such case the GPIO hardware will
not update the interrupt status register (GPI_IS) even if the pin is
configured to trigger an interrupt. It will update GPI_GPE_STS instead and
does not trigger an interrupt.

Allow using such pins as GPIOs, only prevent their usage as interrupts.

We also rename function intel_pad_reserved_for_acpi() to be
intel_pad_acpi_mode() which reflects the actual meaning better.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-27 13:30:56 +01:00
Mika Westerberg 193b40c825 pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt
On Intel Broxton the GPIO hardware consists of several chips that all share
the parent interrupt. It is not possible to handle this by setting chained
handler for each chip (as they will overwrite each other).

To overcome this we need to request the interrupt using devm_request_irq()
and pass IRQF_SHARED with the flags.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-27 13:27:49 +01:00
Mika Westerberg ec879f1272 pinctrl: baytrail: Fix compilation warnings when !CONFIG_PM
When CONFIG_PM is not set we get following compilation warnings:

 warning: ‘byt_gpio_runtime_suspend’ defined but not used [-Wunused-function]
 warning: ‘byt_gpio_runtime_resume’ defined but not used [-Wunused-function]

Fix this by guarding byt_gpio_runtime_suspend()/byt_gpio_runtime_resume()
with #ifdef CONFIG_PM.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-16 22:54:33 +02:00
Mika Westerberg f487bbf309 pinctrl: intel: Fix compilation warning when !CONFIG_PM_SLEEP
We get following warning when CONFIG_PM_SLEEP is not set

  warning: ‘intel_gpio_irq_init’ defined but not used [-Wunused-function]

Since the function is only called from intel_pinctrl_resume() move it
inside CONFIG_PM_SLEEP guard as well.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-16 22:53:40 +02:00
Jonas Gorski 98c85d583a pinctrl: replace trivial implementations of gpio_chip request/free
Replace all trivial request/free callbacks that do nothing but call into
pinctrl code with the generic versions.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Lee Jones <lee@kernel.org>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-16 22:20:21 +02:00
Thomas Gleixner bd0b9ac405 genirq: Remove irq argument from irq flow handlers
Most interrupt flow handlers do not use the irq argument. Those few
which use it can retrieve the irq number from the irq descriptor.

Remove the argument.

Search and replace was done with coccinelle and some extra helper
scripts around it. Thanks to Julia for her help!

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Jiang Liu <jiang.liu@linux.intel.com>
2015-09-16 15:47:51 +02:00