Commit Graph

4 Commits

Author SHA1 Message Date
Chris Brandt a53a28dca4 clk: renesas: r7s9210: Add SPI clocks
Add RSPI clocks for RZ/A2.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-28 09:57:09 +02:00
Chris Brandt 4cb1480f5f clk: renesas: r7s9210: Move table update to separate function
Same functionality, just easier to read.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-26 14:22:05 +02:00
Chris Brandt b9553c13b1 clk: renesas: r7s9210: Convert some clocks to early
The OSTM timer driver for RZ/A2 uses TIMER_OF_DECLARE which requires the
ostm module clocks to be registers early in boot.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-26 14:22:05 +02:00
Chris Brandt fde35c9c7d clk: renesas: cpg-mssr: Add R7S9210 support
Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module
Standby.

The Module Standby HW in the RZ/A series is very close to R-Car HW, except
for how the registers are laid out.
The MSTP registers are only 8-bits wide, there are no status registers
(MSTPSR), and the register offsets are a little different. Since the RZ/A
hardware manuals refer to these registers as the Standby Control Registers,
we'll use that name to distinguish the RZ/A type from the R-Car type.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Rob Herring <robh@kernel.org> # DT bits
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11 12:01:07 +02:00