information available within the IP instead
of reading it from platform data or DT. Some
other useful clean-ups are included too.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJTgGMBAAoJEGFBu2jqvgRN/FAP/2fl2dcX8aYTVY+H7y0r4I65
IpUGqOPktztUI0UgeDtlt1p+B4SBfOIGTP8Zx6PaDD6TQGM2GLv4HFS5yfpVF9vb
OMbCanwHz0GED6UKBbUJQEhaebrTv/M5jdsNrwJ9qMrB7zP7zr1bTDj3G6QJD4+D
n8yUu+HPXD9wtAh263aRPxRFeNfBhJIJtBF3b4HV52KJ0pCPmrwvqpFIahl63AsF
Lrdbt200ZeHFVzkIANN0SSjlUDF9towTCo2ok1VaF0U7JJ1J3WMOJpT/zcrzyYsK
A8Ts8znb/ml7JF94z4Th/dE714QyQcfX/u76skOPRsZUZ9BcQDEX0jNpP3Elgh47
hw8yYj+BJRoCs7tE6o4WpIlCVLgRQglZeyUkTbl4hOAAmvIffoj9MSRk1LDJ/WaC
s3PbT/93KgCOgP/iY0WsSlOPJGGQPHNEB+0O90qHL/e6fh9Kqt3dX1Sf9fj/ZFQ5
x66qTJkDk3SkRzyWFIUyROlEH2toamHKHhQ5v1LUxSPJCekUl3PTUS3GiZtS+PmS
85NSJWwq1Hv9xowKqVS3kkH6gLPkmTTB0uec138RQ/AMHp7SA9DCkShvheyvt1wM
LaPuAmWBci4cALzFo1aeEUEa6ij5Waew0Nm5r9L3kJvMqBCjdLG16DnzXUShFgOq
THYpsGPUdvdUi+JPdps0
=AWLc
-----END PGP SIGNATURE-----
Merge tag 'davinci-for-v3.16/edma' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers
Merge "DaVinci EDMA clean-up for v3.16" from Sekhar Nori:
This series makes edma use configuration information available within
the IP instead of reading it from platform data or DT. Some other useful
clean-ups are included too.
* tag 'davinci-for-v3.16/edma' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: (34 commits)
ARM: edma: Remove redundant/unused parameters from edma_soc_info
ARM: davinci: Remove redundant/unused parameters for edma
ARM: dts: am4372: Remove obsolete properties from edma node
ARM: dts: am33xx: Remove obsolete properties from edma node
dt/bindings: ti,edma: Remove redundant properties from documentation
ARM: edma: Get IP configuration from HW (number of channels, tc, etc)
ARM: edma: Save number of regions from pdata to struct edma
ARM: edma: Remove num_cc member from struct edma
ARM: edma: Remove queue_tc_mapping data from edma_soc_info
ARM: davinci: Remove eDMA3 queue_tc_mapping data from edma_soc_info
ARM: edma: Do not change TC -> Queue mapping, leave it to default.
ARM: edma: Take the number of tc from edma_soc_info (pdata)
ARM: edma: No need to clean the pdata in edma_of_parse_dt()
ARM: edma: Clean up and simplify the code around irq request
dmaengine: edma: update DMA memcpy to use new param element
dmaengine: edma: Document variables used for residue accounting
dmaengine: edma: Provide granular accounting
dmaengine: edma: Make reading the position of active channels work
dmaengine: edma: Store transfer data in edma_desc and edma_pset
dmaengine: edma: Create private pset struct
...
Signed-off-by: Olof Johansson <olof@lixom.net>
make it work. The patch has been tagged for stable.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJTX7HWAAoJEGFBu2jqvgRNJSQP/3zwkXJizhctwlr91OYwJyZ+
uN30iljZvVKf5i+qgp4syjznHOT/yFyS33lG3S9cSSjyjsdZcj5DbOOh2PTEzZd+
josb6bZ+Z6YQBmcYy8V6KuWyEV8UfTr/3wGDb+/cfGfFACD8uxHZo0K/s7p6LCCb
LIo/yzI3DpgrkWYJ7S4kIjz3P+k0gCc3zy1QwbmyWFXYIwREHlgdRAz/M+vjEHyg
tx7HZiewg++dGeSui2PHdxhyTANj6k5emBiGTCOUUBYQ0iI4cGsaT2orzxtgEFRx
Cgd7+/p5Uih2XyC9+7aV6flJoOS2qhsBGvlunVmnd9b7hNxtAtV73I8CEzv3GxDN
hu6WqPnF9ZIO9hPrj6HdrLtYNPJcmRzvaCT9LOCp3q+kxqjGI6QkrDP9hTT0xc4e
9R9/n380048CLsjarfrYgeA1PCDq84I3wbRUUf2Wtgr2vaZufgL6m4cDeZRtzk/s
Ccz+zu4hhxK7NWIH+aze2wcc/8o+l35vaVp2GjGJnh47CAr2Wd65AplWLQhzM3EP
XAiXh2PKAd5fenIlKBIShFI5j+EZ/dSmAqXgYFhXUI7QG35feXeAa8YdbiWSRscq
jqOoDTmKX8eT5p/0i7Dkh9dvHOpiwoHimSHt3yVRQQXAOjj5fyQpjVXBHpHv6+YV
8eY2u5v16Off5qNT4EWH
=eyxH
-----END PGP SIGNATURE-----
Merge tag 'davinci-fixes-for-v3.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers
The patch fixes EDMA crossbar mapping to actually
make it work. The patch has been tagged for stable.
* tag 'davinci-fixes-for-v3.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: common: edma: Fix xbar mapping
to add support for am347x and dra7.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJTa+cJAAoJEBvUPslcq6VzvJUP/3hP6kIthQbv4i5VmGNBXLj9
MWmp3zHR5I1/NEbP90P4Icmiq/gQbKmtU1NBeek7rWDHjT191puJsDSyycpUJ2gY
ii1g1wEaoI0klyx0D5x8N+3V9mNj67z32eRKmPzyUFv9Eb+BzVDX573vwvzJ1y/q
J5CpuZXRO9TQXr/DfgMioGHDTOAVpN8A4/tgeswBGmLRxbOvY2v/20Ex2rr6rF8X
dTu3OVcFq+TbUk7z96r4rSGqKrnWPbKa8N4B6Fpo4iuIbzblGnviN3qCEfaNxUT+
zqNWxqeT0qDimvZikpilwZxFdeMq9SJYUln5h6TPPWenv5Xqbpz2yM1Zk0+W8bm7
r0k4O/PpzKupZ68ElW8VM5/XGzBh4hpATy3D13/JhFT5Xs5mdNH8crMmiTYDIdZu
+dGU2MEL/QCs5OMjZELaKQgzHySCGlPH1k2lCySQMOgPCUrQdp9LSscRfrP1WR67
iCf2Pma9zOgkM2Zzwo0fFU68hrSuovPb6D69e22Q+DUkBdd4JZA9r79LEoA+P7zm
DQRw9FP8IGjBvVxUD4RubdbnvpuyI542eOuCdB6oAyRlh+ynxnoQ39qUNQb3C9ZU
HfYuZR6SSbPSbtlsvfA/79xJoiUyDSOGwco7rwxKuACdSipTedF4dUxHN24zd/kZ
Qnn0kQVVL/AeAtny+ncE
=CY4u
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.16/l3-noc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
Merge "ARM: omap l3-noc bus driver changes for v3.16 merge window, resend" from
Tony Lindgren:
Improvments to omap l3-noc bus driver for v3.16 merge window
to add support for am347x and dra7.
* tag 'omap-for-v3.16/l3-noc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (25 commits)
bus: omap_l3_noc: Add AM4372 interconnect error data
bus: omap_l3_noc: Add DRA7 interconnect error data
bus: omap_l3_noc: introduce concept of submodule
bus: omap_l3_noc: Add information about the context of operation
bus: omap_l3_noc: add information about the type of operation
bus: omap_l3_noc: ignore masked out unclearable targets
bus: omap_l3_noc: improve readability by using helper for slave event parsing
bus: omap_l3_noc: make error reporting and handling common
bus: omap_l3_noc: fix masterid detection
bus: omap_l3_noc: convert flagmux information into a structure
bus: omap_l3_noc: use of_match_data to pick up SoC information
bus: omap_l3_noc: Add support for discountinous flag mux input numbers
bus: omap_l3_noc: convert target information into a structure
bus: omap_l3_noc: move L3 master data structure out
bus: omap_l3_noc: un-obfuscate l3_targ address computation
bus: omap_l3_noc: switch over to relaxed variants of readl/writel
bus: omap_l3_noc: populate l3->dev and use it
bus: omap_l3_noc: remove iclk from omap_l3 struct
bus: omap_l3_noc: rename functions and data to omap_l3
bus: omap_l3_noc: Fix copyright information
...
Signed-off-by: Olof Johansson <olof@lixom.net>
The match tables must be zero-terminated, and Kbuild now helpfully
fails to link the kernel if that isn't the case.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch documents the sysfs properties exposed by the Broadcom GISB
bus arbiter hardware.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch adds the Broadcom GISB arbiter Device Tree binding that is
used on all Broadcom Set-top-box System-on-a-chip.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch adds support for the Broadcom GISB arbiter bus timeout/error
handler. GISB is a proprietary bus used by Broadcom Set Top Box
System-on-a-chip devices (BCM7xxx) which allows multiple masters and
clients to be interfaced with each other.
The bus arbiter offers support for generating two interrupts towards the
host CPU, thus allowing us to "catch" clock gated masters, or masters
being volontarily blocked for powersaving purposes, or do general system
troubleshooting.
We also register a hook with the ARM fault exception handling to allow
printing a more informative message than "imprecise external abort at
0x00000000" for instance.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The GSBI (General Serial Bus Interface) driver controls the overarching
configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and
earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM
functionality in various combinations.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Based on earlier thread "https://lkml.org/lkml/2013/10/7/662" and
discussion at Kernel Summit'2013, it was agreed to create
'driver/soc' for drivers which are quite SOC specific.
Further discussion on the subject is in response to
the earlier version of the patch is here:
http://lwn.net/Articles/588942/
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Olof Johansson <olof@lixom.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
That code used to be in the machine code, but it's more fit here with other
restart hooks.
That will allow to cleanup the machine directory, while waiting for a proper
watchdog driver for the A31.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
The following parameters are no longer needed by the edma driver since the
information can be obtained from the IP's CCCFG register:
n_channel, n_region, n_slot and n_tc.
Remove the n_cc as well since in this context it has no meaning. We have
separate edma_soc_info struct/eDMA3_CC instance so this member does not
make any sense (and the driver no longer uses it).
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The following parameters are no longer needed by the edma driver since the
information can be obtained from the IP's CCCFG register:
n_channel, n_region, n_slot and n_tc.
Remove the initialization of n_cc as well since in this context it has no
meaning. We have separate edma_soc_info struct/eDMA3_CC instance so this
member does not make any sense (and the driver no longer uses it).
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
dma-channels, ti,edma-regions and ti,edma-slots no longer needed in DT since
the the same information is available in the IP's CCCFG register.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
dma-channels, ti,edma-regions and ti,edma-slots no longer needed in DT since
the the same information is available in the IP's CCCFG register.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
From CCCFG register of eDMA3 we can get all the needed information for the
driver about the IP:
Number of channels: NUM_DMACH
Number of regions: NUM_REGN
Number of slots (PaRAM sets): NUM_PAENTRY
Number of TC/EQ: NUM_EVQUE
The ti,edma-regions; ti,edma-slots and dma-channels in DT are
redundant since the very same information can be obtained from the HW.
The mentioned properties are deprecated.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
From CCCFG register of eDMA3 we can get all the needed information for the
driver about the IP:
Number of channels: NUM_DMACH
Number of regions: NUM_REGN
Number of slots (PaRAM sets): NUM_PAENTRY
Number of TC/EQ: NUM_EVQUE
In case when booted with DT or the queue_priority_mapping is not provided
set up a default priority map.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
To be consistent in the code that we take parameters from edma_cc[j] struct
and not randomly from info[j] as well.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The struct edma is allocated per CC bases so the member num_cc does not make
any sense. One CC is one CC, it does not have sub CCs.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
- register sched_clock callback to use clocksource mct-frc
Note that got ack from Daniel
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJTeomJAAoJEA0Cl+kVi2xqKa0QAInbU+rQNv/5Kix76fkXAx1X
68BVp3zIyYL76FsbvnfkVxnxcfU6GsBvX22NzgkTWS4IoRcb3wyW9v16mYatMM+u
3CJ8RuR103DQci83gYrsveYQ4SwYAJC5AZgGg898I5AQ4alx8gIxZ1TGX7GPEL6L
cqzBBaAmGlQ7a94+MOeM94oAMKIXRGm36eZA4/aYcB41jy37o/m88duu+4aCX70Q
mDIGOcuMv71CMbn4IMJaIiapi3eOqRvBdJFaWz0ZttJbdHcLpjRO4tdJNkZ4bpxe
KVKOM3OI7VDYvY2Sz6iRbXesX61YxAL+tacBSRT3m6QWa3NAg/Ns6DBEtc+Y/39x
1YZH823BOlJMh1xb4wkw4fpidCzYXBG42eNGLhf14ITjx1Z06ZnxTQSXn0JKqnCK
q3ZWIfmn3ONPp9Z02UN98vGzAUoa8wAcN4j/nlIiyy/cWJHqRVGPIceSk7TWBUXV
9wmShAA5eBx9OhYaIs4SkjL8AMaEO3X6d6tF0ui9c2Ybt4g6f4Cq429qanUZ+7vT
S3EaBi6oBlbLM6MZgDo4ZBGfAgWIQ9SlQ5U0VDvq58WxLuU7R2vzIq7GHl64nnIH
IWw0V1NFWFXgmswkx0FA5e9Me8/acKXydaFzVOvo1SVWbI/kLLjvRIuSm46ufqzY
WyKrrXOwp/av8sq4Ejwb
=w1kR
-----END PGP SIGNATURE-----
Merge tag 'samsung-drivers' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
Merge "Samsung driver update for 3.16" from Kukjin Kim:
exynos_mct update for v3.16
- register sched_clock callback to use clocksource mct-frc
* tag 'samsung-drivers' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
clocksource: exynos_mct: register sched_clock callback
Signed-off-by: Olof Johansson <olof@lixom.net>
It is ignored by the edma driver since we are just setting back the default
mapping of TC -> Queue.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
There is no need to change the default TC -> Queue mapping. By default the
mapping is: TC0 -> Q0, TC1 -> Q1, etc.
Changing this has no benefits at all and all the board files are just setting
the same mapping back to the HW.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Instead of saving the for loop length, take the num_tc value from the pdata.
In case of DT boot set the n_tc to 3 as it is hardwired in edma_of_parse_dt()
This is a temporary state since upcoming patch(es) will change how we are
dealing with these parameters.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The pdata has been just allocated with devm_kzalloc() in
edma_setup_info_from_dt() and passed to this function.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Get the two interrupt line number at the same time by merging the two
instance of if(node){}else{} places.
replace the &pdev->dev with the already existing dev which makes it possible
to collapse lines with devm_request_irq()
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Merge "Allwinner drivers changes for 3.16" from Maxime Ripard:
Reset drivers for the A31, that have been merged with reset maintainer's
Acked-by.
* 'sunxi/drivers-for-3.16' of https://github.com/mripard/linux:
reset: sunxi: allow MFD subdevices probe
reset: sunxi: document sunxi's reset controllers bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
- mvebu-devbus
- changes need to add support for the orion5x platform
Depends:
- tags/mvebu-fixes-3.15 in the mvebu/fixes branch for:
ce965c3d2e memory: mvebu-devbus: fix the conversion of the bus width
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJTa5xDAAoJEP45WPkGe8ZnEZYP/iPCwDbvoxexpRcaBP+oINc4
rw9VC0E+eujVRJKj5UN3/sji/nV431IDNB3wM+QREPCG7CVkK6pGwKT9gVnBkhZF
03QHKzzTYpVqv+zYv4hGL2CTpQ8I21HSsBFHYeZNNvYDUeqCCGcpdn7I6cf66mxg
Bx5SNVyuz/TrpfKSzF3zSFSwpI+7rKE//Zg4YZG9v8/bsc6qUFb+9/Lu6Hynq/+P
pgHr9YgQP1qhK6YxiFzA1ZAXHY+GdfnK9UuL+oHwcqjcNvV9y3XW3syA5gMK9lBI
8nqQKUw+HjoUTuWURGT7ZLO7DRAODXDSLwHp558VCpjkm0BSMreIGY8d4F87wyzr
J2b8LmL7CwnxOREK8eToh4uz7G6DQwdO4bqppCWUQSn4+ytp8ZG/UG8Yekn83oXq
boHMXldgTfQX4a0JlNLbzfOse3WhNIyAcLeCUwDF0rBwRxdMdoE7Ze34cmumj/wb
Sd1MhhfwMwmUTAb+Bdb6CcKHIkzg6TRwU+C8oWzcex+uMqRFt3gSqKfykso9z2R2
2LyT58XhcKKR9RjZW2UPnMCTxZQVrjBp+VhE72U9HjWX5+Ggqs2GDKxNILuv9fAt
htAq9Ut7czjL3SwBQAdV9A9SJhyXnBVHUJLDkFOubqG37MUPIwLIgoVLu3HqRGia
YMXzkRElm3sSGzkWL4tI
=8W+2
-----END PGP SIGNATURE-----
Merge tag 'mvebu-drivers-3.16' of git://git.infradead.org/linux-mvebu into next/drivers
Merge "ARM: mvebu: driver changes for v3.16" from Jason Cooper:
mvebu driver changes for v3.16
- mvebu-devbus
- changes need to add support for the orion5x platform
* tag 'mvebu-drivers-3.16' of git://git.infradead.org/linux-mvebu:
memory: mvebu-devbus: add a devbus, keep-config property
memory: mvebu-devbus: add Orion5x support
memory: mvebu-devbus: split functions
memory: mvebu-devbus: use _SHIFT suffixes instead of _BIT
memory: mvebu-devbus: use ARMADA_ prefix in defines
ARM: orion5x: fix target ID for crypto SRAM window
memory: mvebu-devbus: fix the conversion of the bus width
Signed-off-by: Olof Johansson <olof@lixom.net>
The current implementation uses sunxi_reset_init function for both early
init and platform device probe.
The sunxi_reset_init function uses DT to retrieve device resources, which
will be an issue if reset controllers are registered from an MFD device
that define resources from mfd_cell definition.
Moreover, we can make of devm functions when we're in the probe context.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Add DT bindings documentation for sunxi's reset controllers.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Add a reset driver for the SOCFPGA platform.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJTWubPAAoJEBmUBAuBoyj0L0UP/1nCHYtmHR4xibfQ0FiUoWWL
im728TuHZHMeCZb5lx0LwZYqOjIOaaSwM0o+VZihibnH8p5e7jHUXHtaq3t/pOoA
TLC4TIWQ8h1SYwlYDseP/6O24drRVKknA/Rj/GUXK7RogCtjgy5c5aK7vE9JcN92
hLCOxAeHfmWSCJL9ieHY4OU6ceIi+fBtoN3Ovf7ddURn43FNlyMFCWYqwIaetUao
8cViL4lJvm1ynoS5itnMvc9KcsTWkwXKEvsklzIMGKgJV4XQO6J/Sv71FUUpNqu/
0EoHRlBnjukhHgMujQkgxsY6o7FtUvopEPThT0dC0XvKFPKspi0Oi0AtZJUQGXsY
zmDuwMoU6b69dfCIJxrY00gDmPYMVM2l9yBmQEXyks7N5AyK7PbUbVAp/MeaVeBI
hZ5ssUJ8wG7NqKk/i8hWWFpD7GAKTD8/M4cpeA3TKnCEmoztHzwZgdTkpBBTN+99
tVY2CeaA9c8B1Doo/vRxCuSqqU0Y8d6KZXKc8OECLnhiqrYTs4YlCEu1S5Wb+kzC
FGzdzeq/6uViT9+DN9LZXlT4cZqpYJn+yOnKjIZceQnBROlS1ZjQ3w9KbkmiPl9E
cnG5G//zTO0iYX7+rR4nz0E53ZKGqbDCGVCBwzmaFoiaQGv54jH+A2MXNi0hK4c2
j6a34K2qrY45RpUeCrYQ
=NuUN
-----END PGP SIGNATURE-----
Merge tag 'socfpga-driver-update-for-3.16' of git://git.rocketboards.org/linux-socfpga-next into next/drivers
Merge "drivers: Add reset driver for SOCFPGA" from Dinh Nguyen:
Add a reset driver for the SOCFPGA platform.
* tag 'socfpga-driver-update-for-3.16' of git://git.rocketboards.org/linux-socfpga-next:
reset: add driver for socfpga
Signed-off-by: Olof Johansson <olof@lixom.net>
Add AM4372 information to handle L3 error.
AM4372 has two clk domains 100f and 200s. Provide flagmux and data
associated with it.
NOTE: Timeout doesn't have STDERRLOG_MAIN register. And per hardware
team, L3 timeout error cannot be cleared the normal way (by setting
bit 31 in STDERRLOG_MAIN), instead it may be required to do system
reset. L3 error handler can't help in such scenarios.
Hence indicate timeout target offset as L3_TARGET_NOT_SUPPORTED as
done for undocumented bits.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
DRA7 is distinctly different from OMAP4 in terms of masters and clock
domain organization. There two main clock domains which is divided as
follows:
<0x44000000 0x1000000> is clk1 and clk2 is the sub clock domain
<0x45000000 0x1000> is clk3
Add all the data needed to handle L3 error handling on DRA7 devices
and mark clk2 as subdomain and provide a compatible flag for
functionality. Other than the data difference the hardware blocks
involved are essentially the same.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: bugfixes and generic improvements, documentation]
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
While OMAP4 and OMAP5 had 3 separate clock domains, DRA7 has only 2
and the first one then is internally divided into 2 sub clock domains.
To better represent this in the driver, we use the concept of submodule.
The address defintions in the devicetree is as per the high level
clock domain(module) base, the sub clockdomain/subdomain which shares
the same register space of a clockdomain is marked in the SoC data as
L3_BASE_IS_SUBMODULE.
L3_BASE_IS_SUBMODULE is used as an indication that it's base address is
the same as the parent module and offsets are considered from the same
base address as they are usually intermingled.
Other than the base address, the submodule is same as a module as it is
functionally so.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
L3 error may be triggered using Debug interface (example JTAG) or
due to other errors, for example an opcode fetch (due to function
pointer or stack corruption) or a data access (due to some other
failure). NOC registers contain additional information to help aid
debug information.
With this, we can enhance the error information to more detailed form:
"
L3 Custom Error: MASTER MPU TARGET L4PER2 (Read): Data Access in User mode
during Functional access
"
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Today we get error such as
L3 Custom Error: MASTER MPU TARGET L4PER2
But since the actual instruction triggerring the error Vs the point
at which we report error may not be aligned, it makes sense to try
and provide additional information - example the type of operation
that was attempted to being performed can help narrow the debug down
further.
This helps provide log such as:
L3 Custom Error: MASTER MPU TARGET L4PER2 (Read)
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Errors that cannot be cleared (determined by reading REGERR register)
are currently handled by masking it. Documentation states that REGERR
"Checks which application/debug error sources are active" - it does not
indicate that this is "interrupt status" - masked out status represented
eventually in the irq line to MPU.
For example:
Lets say module 0 bit 8(0x100) was unclearable, we do the mask it from
generating further errors. However in the following cases:
a) bit 9 of Module 0
OR
b) any bit of Module 1+
occur, the interrupt handler wrongly assumes that the raw interrupt
status of module 0 bit 8 is the root cause of the interrupt, and
returns. This causes unhandled interrupt and resultant infinite
interrupts.
Fix this scenario by storing the events we masked out and masking raw
status with masked ones before identifying and handling the error.
Reported-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Tested-by: Vaibhav Hiremath <hvaibhav@gmail.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Current interrupt handler does the first level parse to identify the
slave and then handles the slave even identification, reporting and
clearing of event as well. It is hence logical to split the handler
into two where the primary handler just parses the flagmux till it
identifies a slave and the slave handling, reporting and clearing is
done in a helper function.
While at it update the documentation in kerneldoc style.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
The logic between handling CUSTOM_ERROR and STANDARD_ERROR is just the
reporting style.
So make it generic, simplify and standardize the reporting with both
master and target information printed to log.
Handle the register address difference for master code for standard
error and custom error as well.
While at it, fix a minor indentation error.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
As per Documentation (OMAP4+), then masterid is infact encoded as
follows:
"L3_TARG_STDERRLOG_MSTADDR[7:0] STDERRLOG_MSTADDR stores the NTTP
master address. The master address is the concatenation of Prefix &
Initiator ConnID. It is defined on 8 bits. The 6 MSBs are used to
distinguish the different initiators."
So, when we matchup currently with the master ID list, we never get a
proper match other than when MPU is the master (thanks to 0).
Now, on other platforms such as AM437x, this tends to be bits[5:0].
Fix this by using the relevant 6MSBits to identify the master ID for
standard and custom errors.
Reported-by: Darren Etheridge <detheridge@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
This allows us to encompass target information and flag mux offset that
points to the target information into a singular structure. This saves
us the need to look up two different arrays indexed by module ID for
information.
This allows us to reduce the static target information allocation to
just the ones that are documented.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
DRA7xx SoC has the same l3-noc interconnect ip (as OMAP4 and OMAP5), but
AM437x SoC has just 2 modules instead of 3 which other SoCs have.
So, stop using direct access of array indices and use of->match data and
simplify implementation to benefit future usage.
While at it, rename a few very generic variables to make them omap
specific. This helps us differentiate from DRA7 and AM43xx data in the
future.
NOTE: None of the platforms that use omap_l3_noc are non-device tree
anymore. So, it is safe to assume OF match here.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: split, refactor and optimize logic]
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
On DRA7, unlike on OMAP4 and OMAP5, the flag mux input numbers used
to indicate the source of errors are not continous. Have a way in the
driver to catch these and WARN the user of the flag mux input thats
either undocumented or wrong.
In the similar vein, Timeout errors in AM43x can't be cleared per h/w
team, neither does it have a STDERRLOG_MAIN to clear the error.
Further, the mux bit offset might not even be indexed into our array
of known mux input description, in which case we'd have a abort.
So, define a static range check for bit description and any definition
which has target_name set to NULL (the ones that are not populated or
ones that are specifically marked in the case of discontinous input
numbers), can handle the same gracefully. Upon occurance of error from
such sources, mask it. Otherwise, we'd have an infinite interrupt
source without any means to clear it.
NOTE: follow on patch ensures that these masked bits are ignored.
[nm@ti.com: rebase, squash and improve]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Currently the target instance information is organized indexed by bit
field offset into multiple arrays.
1. We currently have offsets specific to each target associated with each
clock domains are in seperate arrays:
l3_targ_inst_clk1
l3_targ_inst_clk2
l3_targ_inst_clk3
2. Then they are organized per master index in l3_targ.
3. We have names in l3_targ_inst_name as an array to array of strings
corresponding to the above with offsets.
Simplify the same by defining a structure for information containing
both target offset and name. this is then stored in arrays per domain
and organized into an array indexed off domain.
The array is still indexed based on bit field offset.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Move the L3 master structure out of the static definition to enable
reuse for other SoCs.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
just simplify derefencing that is equivalent.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Currently we use __raw_readl and writel in this driver. Considering
there is no specific need for a memory barrier, replacing writel
with endian-neutral writel_relaxed and replacing __raw_readls with
the corresponding endian-neutral readl_relaxed allows us to have a
standard set of register operations for the driver.
While at it, simplify address computation using variables for
register.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
l3->dev is not populated, so populate it and use it to print information
relevant to the device instead of using a generic pr_*.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
we do not use iclk directly anymore. And, even if we had to, we
should be using pm_runtime APIs to do the same to be completely SoC
independent.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Olof Johansson