This patch adds timer support for the i.MX machine family. This code can
be used on the following machs:
- i.MX1 (tested)
- i.MX2 (i.MX21 (to be tested), i.MX27 (tested))
- i.MX3 (i.MX31 (tested))
TODO: It seems impossible to build a kernel for more than one CPU because the
timer do not follow the platform device rules. So it does only work if
timer 1 can be accessed on all CPUs at the same address.
Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch bases on the one from Daniel Mack. The most important change to
Daniel's patch is to be more generic. This gpio routine supports at least
the i.MX27 and i.MX31 processors.
Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
Acked-by: Daniel Mack <daniel@caiaq.de>
Internal clock path handling for the mxc CPUs.
Changed against the original Freescale code (and against clocklib for example):
- clock rate is always calculated whenever one ask for the current rate
(means struct clk has no more a member called "rate"). So switching the PLL
base frequency will propagate immediately to all other clocks that are
depending on this frequency.
Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
For s3c2412, set parent for clk_erefclk and clk_urefclk.
This allow for example to use xtal or extclk for i2s clock.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Matthieu Castet <matthieu.castet@parrot.com>
Add timer defines for the MUX settings for
each of the PWM timers to add to the per-timer
defines already in the file.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
imx_dma_request_by_prio can return channel number by itself.
No need to supply variable address through parameters.
Also converted all drivers using this function.
Signed-off-by: Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch adds the I-cache invalidation in update_mmu_cache if the
corresponding vma is marked as executable. It also invalidates the
I-cache if a thread migrates to a CPU it never ran on.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Vegard Nossum <vegard.nossum@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ecard_address() is obsolete, and has been marked deprecated since
at least 2.6.12-rc2. All in-tree users have been updated to use
the new approach, so it's time to remove this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Patch mostly by Eric Miao, minor edits by rmk.
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds support for DPLL autoidle control to the OMAP3 clock
framework. These functions will be used by the noncore DPLL enable
and disable code - this is because, according to the CDP code, the
DPLL autoidle status must be saved and restored across DPLL
lock/bypass/off transitions.
N.B.: the CORE DPLL (DPLL3) has three autoidle mode options, rather
than just two. This code currently does not support the third option,
low-power bypass autoidle.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add a new OMAP chip identification interface, omap_chip_id.
omap_chip_id is a structure which contains one bit for each OMAP2/3
CPU type, and on 3430, ES level. For example, the CHIP_IS_OMAP2420
bit is set in omap_chip at boot on an OMAP2420. On OMAP3430ES2, both
CHIP_IS_OMAP3430 and CHIP_IS_OMAP3430ES2 bits are set.
omap_chip is set in mach-omap2/id.c by _set_omap_chip(). Other
code should use the omap_chip_is() function to test against omap_chip.
Also, clean up id.c by splitting some code out of
omap_check_revision() into its own function, _set_system_rev(); and
converting some debug printk()s into pr_debug().
Second revision.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
New struct omap_globals contains the omap processor specific
module bases. Use omap_globals to set the various base addresses
to make detecting omap chip type simpler.
Also introduce OMAP1_IO_ADDRESS and OMAP2_IO_ADDRESS for future multi-omap
patches.
Signed-off-by: Tony Lindgren <tony@atomide.com>
This does not play nicely with multi-omap as it cannot be replaced
by a function in io.c for omaps with different IO bases.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Change omap USB code to use omap_read/write instead of __REG for multi-omap
Cc: David Brownell <david-b@pacbell.net>
Cc: linux-usb@vger.kernel.org
Cc: i2c@lm-sensors.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
Change omap_cf.c and omap_nor.c to use omap_readw/writew instead of __REG.
This is needed for multi-omap in the future.
Cc: David Brownell <david-b@pacbell.net>
Cc: linux-pcmcia@lists.infradead.org
Cc: linux-mtd@lists.infradead.org
Signed-off-by: Tony Lindren <tony@atomide.com>
debugfs can provide the infrastructure to trace the dependencies of
clock tree hierarchy quite visibly. This patch enables to keep track
of clock tree hierarchy and expose their attributes under each clock
directry as below:
omap:~# tree -d -L 2 /debug/clock/omap_32k_fck/
/debug/clock/omap_32k_fck/
|-- gpt10_fck
|-- gpt11_fck
|-- gpt1_fck
|-- per_32k_alwon_fck
| |-- gpio2_fck
| |-- gpio3_fck
| |-- gpio4_fck
| |-- gpio5_fck
| |-- gpio6_fck
| `-- wdt3_fck
|-- ts_fck
`-- wkup_32k_fck
|-- gpio1_fck
`-- wdt2_fck
14 directories
omap:~# tree /debug/clock/omap_32k_fck/gpt10_fck/
/debug/clock/omap_32k_fck/gpt10_fck/
|-- flags
|-- rate
`-- usecount
0 directories, 3 files
Although, compared with David Brownell's small patch, this may look
bit overkilling, I expect that this debugfs can deal with other PRCM
complexities at the same time. For example, powerdomain dependencies
can be expressed by using symbolic links of these clocks if
powerdomain supports dubgfs as well.
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
If boards with different NR_IRQS are compiled together, tons of
compiler warnings are emitted about redefining NR_IRQS.
This patch fixes the problem by adding up NR_IRQS in a common place.
Patch also removes quite a bit of now unnecessary code.
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch transform mcbsp code to use platform data
from arch/arm/plat-omap/devices.c
It also gets ride of ifdefs on mcbsp.c code.
To do it, a platform data structure was defined.
Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Remove __REG access in DMA code, use dma_read/write instead:
- dynamically set the omap_dma_base based on the omap type
- omap_read/write becomes dma_read/write
- dma channel registers are read with dma_ch_read/write
Cc: David Brownell <david-b@pacbell.net>
Cc: linux-usb@vger.kernel.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add symbolic constants for OMAP3430 base addresses; include that file
in hardware.h.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch optimizes the timer load and start sequence. By combining the
load and start a needless posted wait can be removed from the system timer
execution path.
* Before patch register writes are taking up .078% @ 500MHz during idle.
Address |total |min |max |avr |count|ratio%
old\process\default_idle|7.369s |0.0us|999.902ms|14.477ms|509. |62.661%
ld\Global\cpu_v7_do_idle|4.265s |0.0us|375.786ms|24.374ms|175. |36.270%
(UNKNOWN)|17.503ms|0.us|531.080us|5.119us|3419. |0.148%
r\omap_dm_timer_set_load|8.135ms|0.0us|79.887us|15.065us|540. |0.069% <--
\vmlinux-old\Global\_end|2.023ms|0.0us|4.000us|0.560us|3613. |0.017%
-old\Global\__raw_readsw|1.962ms|0.0us|108.610us|9.167us|214. |0.016%
old\smc91x\smc_interrupt|1.353ms|0.0us|10.212us|2.348us|576. |0.011%
s/namei\__link_path_walk|1.161ms|0.0us|4.310us|0.762us| 1524. |0.009%
\omap_dm_timer_write_reg|1.085ms|0.0us|126.150us|2.153us|504. |0.009% <--
* After patch timer functions do not show up in top listings for long captures.
Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Some SoCs need a different chip_delay value.
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Acked-by: Jörn Engel <joern@logfs.org>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
This patch allows booting Kirkwood with the L2 in writeback mode,
by reading the WT override bit from the L2 config register and
passing that into the Feroceon L2 init routine, instead of assuming
that the WT override bit will always be set
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This converts arm to use the new helpers for smp_call_function() and
friends, and adds support for smp_call_function_single().
Fixups and testing done by Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
Record the address of the mcount call-site. Currently all archs except sparc64
record the address of the instruction following the mcount call-site. Some
general cleanups are entailed. Storing mcount addresses in rec->ip enables
looking them up in the kprobe hash table later on to check if they're kprobe'd.
Signed-off-by: Abhishek Sagar <sagar.abhishek@gmail.com>
Cc: davem@davemloft.net
Cc: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
The Discovery Duo (MV78xx0) has two x4 PCIe ports which can either
be used in x4 mode or in quad x1 mode. This patch adds an accessor
function to the generic plat-orion PCIe handling code to detect in
which of the two modes we're running (which is determined by strap
pins and/or configured by the bootloader).
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
interface, and IDMA/XOR engines, and depending on the model, also
features one or two Gigabit Ethernet interfaces, two SATA II
interfaces, one or two TWSI interfaces, one or two UARTs, a
TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
an SDIO interface.
This patch adds supports for the Marvell DB-88F6281-BP Development
Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
enabling support for the PCIe interface, the USB interface, the
ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
UARTs, and the NAND controller.
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This patch adds support for the unified Feroceon L2 cache controller
as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo
families of ARM SoCs.
Note that:
- Page table walks are outer uncacheable on Kirkwood and Discovery
Duo, since the ARMv5 spec provides no way to indicate outer
cacheability of page table walks (specifying it in TTBR[4:3] is
an ARMv6+ feature).
This requires adding L2 cache clean instructions to
proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to
tlbflush.h ({flush,clean}_pmd_entry()). The latter case is handled
by defining a new TLB type (TLB_FEROCEON) which is almost identical
to the v4wbi one but provides a TLB_L2CLEAN_FR flag.
- The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2
range by MVA' and 'invalidate L2 range by MVA') operations, and this
patch uses those range operations for all Linux outer cache
operations, as they are faster than the regular per-line operations.
L2 range operations are not interruptible on this hardware, which
avoids potential livelock issues, but can be bad for interrupt
latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which
allows you to select the maximum range size to operate on at once.
(Valid range is between one cache line and one 4KiB page, and must
be a multiple of the line size.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This patch adds support for the L1 D cache range operations that
are supported by the Marvell Discovery Duo and Marvell Kirkwood
ARM SoCs.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Acked-by: Saeed Bishara <saeed@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Some Feroceon-based SoCs have an MBUS bridge interrupt controller
that requires writing a one instead of a zero to clear edge
interrupt sources such as timer expiry.
This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform
code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or
BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This define isn't used anywhere in the kernel tree -- nuke it.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <linux@arm.linux.org.uk>
The implementation for memory copy functions on ARM had a (disabled)
provision for aligning the source pointer before loading registers with
data. Turns out that aligning the _destination_ pointer is much more
useful, as the read side is already sufficiently helped with the use of
preload.
So this changes the definition of the CALGN() macro to target the
destination pointer instead, and turns it on for Feroceon processors
where the gain is very noticeable.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This adds the definition for the third USB port control register UP3OCR. It is
used on the EZX GSM mobile phones.
Signed-off-by: Stefan Schmidt <stefan@datenfreihafen.org>
Acked-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Macros like Fld() or FShft used in regs-lcd.h are defined in bitfield.h, but
the latter is not included.
Also fix one whitespace issue while being there.
Signed-off-by: Antonio Ospite <ao2@openezx.org>
Signed-off-by: Stefan Schmidt <stefan@datenfreihafen.org>
Acked-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This is basically s/at91_nand/atmel_nand/g with some manual inspection.
Signed-off-by: Håvard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
The AT91 NAND driver needs just a few tiny modifications to work on
AVR32 as well. Rename it atmel_nand to reflect this.
Also move the ECC register definitions into drivers/mtd/nand since they
are only useful to the atmel_nand driver, and get rid of the useless
filename at the top of each file.
Signed-off-by: Håvard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
The power manager and core clock registers aren't present in PXA3
CPUs. Move them out of pxa-regs.h into pxa2xx-regs.h, and include
pxa2xx-regs.h where necessary.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Adds support for the USB High Speed Device Port on the AT91SAM9RL
system on chip. The AT91SAM9RL uses the same UDPHS IP as the AVR32 and
the AT91CAP9 (atmel_usba_udc driver).
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This is patch 2 of 2 adding support for the USB High Speed Device Port
on the AT91CAP9 system on chip. The AT91CAP9 uses the same UDPHS IP
as the AVR32 and the AT91SAM9RL.
This patch declares the UDPHS ressources in the at91cap9 (cpu and
adk board) files, wires up the atmel_usba_udc driver to them,
and activates the driver in the defconfig.
Signed-off-by: Stelian Pop <stelian@popies.net>
Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Acked-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This is patch 1 of 2 adding support for the USB High Speed Device Port
on the AT91CAP9 system on chip. The AT91CAP9 uses the same UDPHS IP
as the AVR32 and the AT91SAM9RL.
This patch makes the generic AT91 adaptations, mainly dealing with
the addition of the UDPHS UTMI clock.
Signed-off-by: Stelian Pop <stelian@popies.net>
Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Acked-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add support for three AT91-based boards available from Calao Systems:
USB_A9260, USB_A9263 and QIL_A9260.
Signed-off-by: Grégory Hermant <gregory.hermant@calao-systems.com>
Signed-off-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Acked-by: Richard Purdie <rpurdie@rpsys.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The current __raw_write_can_lock macro tests whether the lock can be
locked by checking if it is equal to 0x80000000, whereas the lock
should be lockable if its value is 0 i.e. unlocked state is
represented by 0. Hence the macro should test the value of lock
against 0 and not 0x80000000.
Signed-off-by: Surinder Pal Singh <srplsnh@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
PSKTSEL can be routed to GPIO pin 104. This configuration is used by
HP iPAQ hx4700.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Acked-by: Jrgen Schindele <linux@schindele.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Some additional alternate gpio definitions relating
to FFUART and USB on the pxa27x. These are used on
the xbow imote2 platform.
Signed-off-by: Jonathan Cameron <jic23@cam.ac.uk>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Follow suit from kprobe implementations on other archs and make kretprobe_trampoline non-static. Ftrace implmentation (more specifically, kernel/trace/trace.c) requires access to it (see-> http://kerneltrap.org/mailarchive/linux-kernel/2008/5/27/1955234).
Signed-off-by: Abhishek Sagar <sagar.abhishek@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
AT91 has one include loop in its header files:
include/asm-arm/io.h <- include/asm-arm/arch-at91/io.h <-
include/asm-arm/io.h
Circular include dependencies are dangerous since they can result in
inconsistent definitions being provided to other code, especially if
'#ifndef' constructs are used.
Solve this by removing the offending includes. Built tested using my
AT91 configuration.
Acked-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
It's not very critical because __REG2 isn't used in assembler code
currently.
Additionally some white space noise is fixed.
Signed-off-by: Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
atags.c was the only user of KEXEC_BOOT_PARAMS_SIZE and kexec.h
was only included to get that definition.
Signed-off-by: Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
Acked-by: Uli Luckas <u.luckas@road.de>
OMAP has two include loops in its header files:
asm-arm/hardware.h <- asm-arm/arch-omap/io.h <-
asm-arm/arch-omap/hardware.h <- asm-arm/hardware.h
asm-arm/arch-omap/board-palmte.h <-
asm-arm/arch-omap/hardware.h <- asm-arm/hardware.h <-
asm-arm/arch-omap/gpio.h <- asm-arm/arch-omap/board-palmte.h
Circular include dependencies are dangerous since they can result in
inconsistent definitions being provided to other code, especially if
'#ifndef' constructs are used.
Solve these by removing the offending includes, and add additional
includes where necessary.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
For the simple read_cpuid() macro case the variable processor_id has
no definition on use of the macro. Add an extern for it. Move all the
processor ID macros into the #ifndef __ASSEMBLEY__ block.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The non-MMU case also needs the type definition of pgtable_t.
So move it out of a CONFIG_MMU conditional section.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/plat-omap/clock.c:397: warning: "struct cpufreq_frequency_table" declared inside parameter list
arch/arm/plat-omap/clock.c:397: warning: its scope is only this definition or declaration, which is probably not what you want
arch/arm/plat-omap/clock.c: In function `clk_init_cpufreq_table':
arch/arm/plat-omap/clock.c:402: error: structure has no member named `clk_init_cpufreq_table'
arch/arm/plat-omap/clock.c:403: error: structure has no member named `clk_init_cpufreq_table'
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now that all drivers using it are gone, remove the old ARM RTC library.
Acked-by: Alessandro Zummo <a.zummo@towertech.it>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
collie.h:
* add some meaningfull names to some gpios
collie.c:
* initialize cpu registers correctly
Signed-off-by: Thomas Kunze <thommycheck@gmx.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The PXA25x and PXA27x USB device controller register definitions are
different. Currently, they live side by side in pxa-regs.h, but only
one set is available depending on the setting of PXA25x or PXA27x.
This means that if we build to support both PXA25x and PXA27x, the
PXA27x definitions are unavailable, even to PXA27x specific code.
Remove these definitions from pxa-regs.h, and place them in separate
files. Include these files where appropriate.
Note: according to the dependencies in drivers/usb/gadget/Kconfig,
we do not support the UDC on PXA27x nor PXA3xx CPUs, so remove the
platform devices from pxa27x.c and pxa3xx.c.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Parenthesis fix in include/asm-arm/arch-omap/control.h
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
irqs.h:
* rename IRQ_LOCOMO_SPI_OVRN to IRQ_LOCOMO_SPI_REND
locomo.h:
* add some definition for locomo spi controller
* correct some errors
locomo.c:
* correct some errors
* add set_type for locomo gpio irq chip
Signed-off-by: Thomas Kunze <thommycheck@gmx.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
dyntick is superseded by the clocksource/clockevent infrastructure,
using the NO_HZ configuration option. No one implements dyntick on
ARM anymore, so it's pointless keeping it around. Remove dyntick
support.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add the omap2_set_globals_{242x,243x,343x}() functions. These
functions are called early upon boot in the map_io() functions in the
board-specific init files.
This patch was accidentally left out of the earlier series.
This fixes omap2 booting as noted by Kyungmin Park <kmpark@infradead.org>.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kyungmin Park <kmpark@infradead.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Related to d3930614e6.
RCSR is only present on PXA2xx CPUs, not on PXA3xx CPUs. Therefore,
we should not be unconditionally writing to RCSR from generic code.
Since we now clear the RCSR status from the SoC specific PXA PM code
and before reset in the arch_reset() function, the duplication in
the corgi, poodle, spitz and tosa code can be removed.
Acked-by: Richard Purdie <rpurdie@rpsys.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Each time a pxa type cpu went in suspend, a portion of
kmalloc memory was corrupted.
The issue was an incorrect length allocation introduced by
the commit 711be5ccfe for
the save registers array (=> overflow).
Signed-off-by: Robert Jarzmik <rjarzmik@free.fr>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This modifies <asm-arm/types.h> to use the <asm-generic/int-*.h>
generic include files.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Lennert Buytenhek <kernel@wantstofly.org>
Cc: Ben Dooks <ben-linux@fluff.org>
Trying to compile a kerel for ARCH_CO285 fails with the following error:
<-- snip -->
...
CC arch/arm/mach-footbridge/dc21285.o
/home/bunk/linux/kernel-2.6/git/linux-2.6/arch/arm/mach-footbridge/dc21285.c:
In function 'dc21285_base_address':
/home/bunk/linux/kernel-2.6/git/linux-2.6/arch/arm/mach-footbridge/dc21285.c:54: error: 'PCICFG0_BASE' undeclared (first use in this function)
/home/bunk/linux/kernel-2.6/git/linux-2.6/arch/arm/mach-footbridge/dc21285.c:54: error: (Each undeclared identifier is reported only once
/home/bunk/linux/kernel-2.6/git/linux-2.6/arch/arm/mach-footbridge/dc21285.c:54: error: for each function it appears in.)
/home/bunk/linux/kernel-2.6/git/linux-2.6/arch/arm/mach-footbridge/dc21285.c:57: error: 'PCICFG1_BASE' undeclared (first use in this function)
/home/bunk/linux/kernel-2.6/git/linux-2.6/arch/arm/mach-footbridge/dc21285.c:
In function 'dc21285_scan_bus':
/home/bunk/linux/kernel-2.6/git/linux-2.6/arch/arm/mach-footbridge/dc21285.c:286: error: implicit declaration of function 'pci_scan_bus'
...
make[2]: *** [arch/arm/mach-footbridge/dc21285.o] Error 1
<-- snip -->
This does not seem to be a recent breakage.
The ARCH_CO285 support is old - kernel 2.2.0 contains first traces of
it, an it seems to have been pretty complete in later 2.2 kernels.
Since it seems to be completely dead code now this patch therefore
removes it.
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rename div64_64 to div64_u64 to make it consistent with the other divide
functions, so it clearly includes the type of the divide. Move its definition
to math64.h as currently no architecture overrides the generic implementation.
They can still override it of course, but the duplicated declarations are
avoided.
Signed-off-by: Roman Zippel <zippel@linux-m68k.org>
Cc: Avi Kivity <avi@qumranet.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Jeff Dike <jdike@addtoit.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Patrick McHardy <kaber@trash.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Reasons:
1. straight forward: the name "LCD_COLOR_DSTN_16BPP" is much better
than "LCCR0_Pas | LCCR0_Color | LCCR0_Dual"
2. by defining LCD connection types as constants, it allows only
valid possibilities
3. by removing the dependency of register bits definitions, those
can be later moved into the body of pxafb.c, instead of having
a regs-lcd.h around
Currently, only lubbock, mainstone, zylonite and littleton have been
modified to support these types (see coming patches after this).
Other platforms are encouraged to change their way describing the
LCD controller connections.
Signed-off-by: eric miao <eric.miao@marvell.com>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This is part of the effort moving peripheral registers outside of pxa-regs.h,
and using ioremap() make it possible the same IP can be re-used on different
processors with different registers space
As a result, the fixed mapping in pxa_map_io() is removed.
The regs-lcd.h can actually moved to where closer to pxafb.c but some of its
bit definitions are directly used by various platform code, though this is not
a good style.
Signed-off-by: eric miao <eric.miao@marvell.com>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Unaligned access is ok for the following arches:
cris, m68k, mn10300, powerpc, s390, x86
Arches that use the memmove implementation for native endian, and
the byteshifting for the opposite endianness.
h8300, m32r, xtensa
Packed struct for native endian, byteshifting for other endian:
alpha, blackfin, ia64, parisc, sparc, sparc64, mips, sh
m86knommu is generic_be for Coldfire, otherwise unaligned access is ok.
frv, arm chooses endianness based on compiler settings, uses the byteshifting
versions. Remove the unaligned trap handler from frv as it is now unused.
v850 is le, uses the byteshifting versions for both be and le.
Remove the now unused asm-generic implementation.
Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com>
Acked-by: David S. Miller <davem@davemloft.net>
Cc: <linux-arch@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This patch implements a set of Feroceon-specific
{copy,clear}_user_page() routines that perform more optimally than
the generic implementations. This also deals with write-allocate
caches (Feroceon can run L1 D in WA mode) which otherwise prevents
Linux from booting.
[nico: optimized the code even further]
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Sylver Bruneau <sylver.bruneau@googlemail.com>
Tested-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
The ioremap() optimization used for internal register didn't cope
with the fact that paddr + size can wrap to zero if the area extends
to the end of the physical address space.
Issue isolated by Sylver Bruneau <sylver.bruneau@googlemail.com>.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
s390 for one, cannot implement VM_MIXEDMAP with pfn_valid, due to their memory
model (which is more dynamic than most). Instead, they had proposed to
implement it with an additional path through vm_normal_page(), using a bit in
the pte to determine whether or not the page should be refcounted:
vm_normal_page()
{
...
if (unlikely(vma->vm_flags & (VM_PFNMAP|VM_MIXEDMAP))) {
if (vma->vm_flags & VM_MIXEDMAP) {
#ifdef s390
if (!mixedmap_refcount_pte(pte))
return NULL;
#else
if (!pfn_valid(pfn))
return NULL;
#endif
goto out;
}
...
}
This is fine, however if we are allowed to use a bit in the pte to determine
refcountedness, we can use that to _completely_ replace all the vma based
schemes. So instead of adding more cases to the already complex vma-based
scheme, we can have a clearly seperate and simple pte-based scheme (and get
slightly better code generation in the process):
vm_normal_page()
{
#ifdef s390
if (!mixedmap_refcount_pte(pte))
return NULL;
return pte_page(pte);
#else
...
#endif
}
And finally, we may rather make this concept usable by any architecture rather
than making it s390 only, so implement a new type of pte state for this.
Unfortunately the old vma based code must stay, because some architectures may
not be able to spare pte bits. This makes vm_normal_page a little bit more
ugly than we would like, but the 2 cases are clearly seperate.
So introduce a pte_special pte state, and use it in mm/memory.c. It is
currently a noop for all architectures, so this doesn't actually result in any
compiled code changes to mm/memory.o.
BTW:
I haven't put vm_normal_page() into arch code as-per an earlier suggestion.
The reason is that, regardless of where vm_normal_page is actually
implemented, the *abstraction* is still exactly the same. Also, while it
depends on whether the architecture has pte_special or not, that is the
only two possible cases, and it really isn't an arch specific function --
the role of the arch code should be to provide primitive functions and
accessors with which to build the core code; pte_special does that. We do
not want architectures to know or care about vm_normal_page itself, and
we definitely don't want them being able to invent something new there
out of sight of mm/ code. If we made vm_normal_page an arch function, then
we have to make vm_insert_mixed (next patch) an arch function too. So I
don't think moving it to arch code fundamentally improves any abstractions,
while it does practically make the code more difficult to follow, for both
mm and arch developers, and easier to misuse.
[akpm@linux-foundation.org: build fix]
Signed-off-by: Nick Piggin <npiggin@suse.de>
Acked-by: Carsten Otte <cotte@de.ibm.com>
Cc: Jared Hulbert <jaredeh@gmail.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Add struct ide_io_ports and use it instead of `unsigned long io_ports[]`
in ide_hwif_t.
* Rename io_ports[] in hw_regs_t to io_ports_array[].
* Use un-named union for 'unsigned long io_ports_array[]' and 'struct
ide_io_ports io_ports' in hw_regs_t.
* Remove IDE_*_OFFSET defines.
v2:
* scc_pata.c build fix from Stephen Rothwell.
v3:
* Fix ctl_adrr typo in Sparc-specific part of ns87415.c.
(Noticed by Andrew Morton)
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
The kernel should clean stale bits from reset status, so that
they won't confuse the bootloader.
Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The patch kills the use of IRQ_GPIO() and adds
#if NR_IRQS < (IT8152_LAST_IRQ+1) statement.
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add support to disable ECC checking for a given chip
when passed by the board via the platform data.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Add support for the ECC layout to be passed via the
platform data specified by the board.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
If a block's ecc field is all 0xff, then ignore the ECC
correction. This is for systems where some of the blocks,
such as the initial cramfs are written without ECC and
need to be loaded on start.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
This is preliminary since:
1. It supports only _one_ chip select at the moment. As there is no
existing platforms available using two chip selects of the NAND
controller, it shall really not include code for supporting the
2nd chip select for now, as such code cannot be verified.
2. It resorts to the default and simpliest memory based badblock
table
3. Only limited types of nand flash are currently supported. Most
PXA3xx processors come with on-chip NAND flash dies, so there
isn't much flexibility for other types of NAND.
4. The NAND controller should be configured to detect the device's
ID, thus making it difficult to use nand_scan_ident() to assist
the detection process (though it's not impossible)
TODO: fix all the above limitations of cuz :-)
Signed-off-by: eric miao <eric.miao@marvell.com>
Cc: Sergey Podstavin <spodstavin@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/drzeus/mmc: (26 commits)
mmc: sdio_ops.c should #include "sdio_ops.h"
mmc: proper prototypes for mmc_attach_*()
mmc: make __mmc_release_bus() static
sdhci: improve no card, no reset quirk
MMC: OMAP: Do not busy wait for end of command for ever
MMC: OMAP: Start new commands from work queue instead of irq
MMC: OMAP: Lazy clock shutdown
MMC: OMAP: Move failing command abortion to workqueue
MMC: OMAP: Use tasklet instead of workqueue for cover switch notification
MMC: OMAP: Check the get_cover_state function pointer if not set
MMC: OMAP: Using setup_timer instead of init_timer
MMC: OMAP: Abort stuck commands
MMC: OMAP: General cleanup for MMC multislot support
MMC: OMAP: Power functions modified to MMC multislot support
MMC: OMAP: Fix timeout calculation for MMC multislot support
MMC: OMAP: New release dma and abort xfer functions
MMC: OMAP: Add back cover switch support
MMC: OMAP: Introduce new multislot structure and change driver to use it
MMC: OMAP: Remove cover switch handling to allow adding multislot support
MMC: OMAP: Fix the BYTEBLOCK capability removal
...
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/juhl/trivial: (24 commits)
DOC: A couple corrections and clarifications in USB doc.
Generate a slightly more informative error msg for bad HZ
fix typo "is" -> "if" in Makefile
ext*: spelling fix prefered -> preferred
DOCUMENTATION: Use newer DEFINE_SPINLOCK macro in docs.
KEYS: Fix the comment to match the file name in rxrpc-type.h.
RAID: remove trailing space from printk line
DMA engine: typo fixes
Remove unused MAX_NODES_SHIFT
MAINTAINERS: Clarify access to OCFS2 development mailing list.
V4L: Storage class should be before const qualifier (sn9c102)
V4L: Storage class should be before const qualifier
sonypi: Storage class should be before const qualifier
intel_menlow: Storage class should be before const qualifier
DVB: Storage class should be before const qualifier
arm: Storage class should be before const qualifier
ALSA: Storage class should be before const qualifier
acpi: Storage class should be before const qualifier
firmware_sample_driver.c: fix coding style
MAINTAINERS: Add ati_remote2 driver
...
Fixed up trivial conflicts in firmware_sample_driver.c
The C99 specification states in section 6.11.5:
The placement of a storage-class specifier other than at the
beginning of the declaration specifiers in a declaration is an
obsolescent feature.
Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Signed-off-by: Jesper Juhl <jesper.juhl@gmail.com>
Alternate function and direction setting is now handled
by the MFP config code or the generic GPIO API.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch adds a driver for the Quick Capture Interface on the PXA270.
It is based on the original driver from Intel, but has been re-worked
multiple times since then, now it also supports the V4L2 API.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Adds support for the generic GPIO lib to the EP93xx family. The gpio
handling code has been moved from core.c to a new file called gpio.c.
The GPIO based IRQ code has not been changed.
Signed-off-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This adds support for two more leds:
the wlan one (found in SL-6000W and SL-6000L) and
the blutooth one (found in SL-6000W).
Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now that scoop gpio's are converted to generic_gpio,
tosascoop_device and tosascoop_jc_device don't have
to be exported.
Also make tosa_gpio_* static
Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Set up the IRQ line for the WM9713 device on the Zylonite.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: eric miao <eric.y.miao@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now as the scoop pins are covered by the generic gpio API,
we can use leds-gpio driver instead of special leds-tosa.
Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Convert set/reset_scoop_gpio to generic gpio calls.
This patch depends on the pxaficp_ir hooks patch.
Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Let platform do some specific initialisation and cleanup
things during pxaficp_ir probing and removing. E.g. this
can be usefull to request/free gpios used by the platform
to control the transceiver.
Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch fixes misprint in definition of CICR1_RGBT_CONV in include/asm-arm/arch-pxa/pxa-regs.h
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
All magician devices I've encountered so far have featured the Toppoly
TD028STEB1 display, so the Samsung LTP280QV support is untested.
The power-on sequence is not correct because pxafb doesn't yet support
enabling the LCD controller in the middle of the it.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
needed for power management (audio, BT, charging, GSM, LCD, SD), GSM, flash and SD operation and audio routing.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
PXA GPIO definitions were split from pxa-regs.h into pxa2xx-gpio.h.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch implements support for Gumstix-F flash, udc and mci. Fixes since the last time are:
- Steve Sakoman as maintainer
- cleanup for udc and mci setup
Signed-off-by: Jaya Kumar <jayakumar.lkml@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Keypad registers are now fully defined within pxa27x-keypad.c, no
need to keep those definitions in pxa-regs.h
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
also update the clk definitions in pxa27x and pxa3xx.
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Changes include:
1. rename MFP_LPM_WAKEUP_ENABLE into MFP_LPM_CAN_WAKEUP to indicate
the board capability of this pin to wakeup the system
2. add gpio_set_wake() and keypad_set_wake() to allow dynamically
enable/disable wakeup from GPIOs and keypad GPIO
* these functions are currently kept in mfp-pxa2xx.c due to their
dependency to the MFP configuration
3. pxa2xx_mfp_config() only gives early warning if MFP_LPM_CAN_WAKEUP
is set on incorrect pins
So that the GPIO's wakeup capability is now decided by the following:
a) processor's capability: (only those GPIOs which have dedicated
bits within PWER/PRER/PFER can wakeup the system), this is
initialized by pxa{25x,27x}_init_mfp()
b) board design decides:
- whether the pin is designed to wakeup the system (some of
the GPIOs are configured as other functions, which is not
intended to be a wakeup source), by OR'ing the pin config
with MFP_LPM_CAN_WAKEUP
- which edge the pin is designed to wakeup the system, this
may depends on external peripherals/connections, which is
totally board specific; this is indicated by MFP_LPM_EDGE_*
c) the corresponding device's (most likely the gpio_keys.c) wakeup
attribute:
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Pin configuration on pxa{25x,27x} has now separated from generic GPIO
into dedicated mfp-pxa2xx.c by this patch. The name "mfp" is borrowed
from pxa3xx and is used here to alert the difference between the two
concepts: pin configuration and generic GPIOs. A GPIO can be called
a "GPIO" _only_ when the corresponding pin is configured so.
A pin configuration on pxa{25x,27x} is composed of:
- alternate function selection (or pin mux as commonly called)
- low power state or sleep state
- wakeup enabling from low power mode
The following MFP_xxx bit definitions in mfp.h are re-used:
- MFP_PIN(x)
- MFP_AFx
- MFP_LPM_DRIVE_{LOW, HIGH}
- MFP_LPM_EDGE_*
Selecting alternate function on pxa{25x, 27x} involves configuration
of GPIO direction register GPDRx, so a new bit and MFP_DIR_{IN, OUT}
are introduced. And pin configurations are defined by the following
two macros:
- MFP_CFG_IN : for input alternate functions
- MFP_CFG_OUT : for output alternate functions
Every configuration should provide a low power state if it configured
as output using MFP_CFG_OUT(). As a general guideline, the low power
state should be decided to minimize the overall power dissipation. As
an example, it is better to drive the pin as high level in low power
mode if the GPIO is configured as an active low chip select.
Pins configured as GPIO are defined by MFP_CFG_IN(). This is to avoid
side effects when it is firstly configured as output. The actual
direction of the GPIO is configured by gpio_direction_{input, output}
Wakeup enabling on pxa{25x, 27x} is actually GPIO based wakeup, thus
the device based enable_irq_wake() mechanism is not applicable here.
E.g. invoking enable_irq_wake() with a GPIO IRQ as in the following
code to enable OTG wakeup is by no means portable and intuitive, and
it is valid _only_ when GPIO35 is configured as USB_P2_1:
enable_irq_wake( gpio_to_irq(35) );
To make things worse, not every GPIO is able to wakeup the system.
Only a small number of them can, on either rising or falling edge,
or when level is high (for keypad GPIOs).
Thus, another new bit is introduced to indicate that the GPIO will
wakeup the system:
- MFP_LPM_WAKEUP_ENABLE
The following macros can be used in platform code, and be OR'ed to
the GPIO configuration to enable its wakeup:
- WAKEUP_ON_EDGE_{RISE, FALL, BOTH}
- WAKEUP_ON_LEVEL_HIGH
The WAKEUP_ON_LEVEL_HIGH is used for keypad GPIOs _only_, there is
no edge settings for those GPIOs.
These WAKEUP_ON_* flags OR'ed on wrong GPIOs will be ignored in case
that platform code author is careless enough.
The tradeoff here is that the wakeup source is fully determined by
the platform configuration, instead of enable_irq_wake().
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
two reasons:
1. GPIO namings and their mode definitions are conceptually not part
of the PXA register definitions
2. this is actually a temporary move in the transition of PXA2xx to
use MFP-alike APIs (as what PXA3xx is now doing), so that legacy
code will still work and new code can be added in step by step
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This makes the code better organized and simplified a bit. The change
will lose a bit of performance when performing IRQ ack/mask/unmask,but
that's not too much after checking the result binary.
This patch also removes the ugly #ifdef CONFIG_PXA27x .. #endif by
carefully not to access those pxa{27x,3xx} specific registers, this
is done by keeping an internal IRQ number variable. The pxa-regs.h
is also modified so registers for IRQ > PXA_IRQ(31) are made public
even if CONFIG_PXA{27x,3xx} isn't defined (for pxa25x's sake)
The incorrect assumption in the original code that internal irq starts
from 0 is also corrected by comparing with PXA_IRQ(0).
"struct sys_device" for the IRQ are reduced into one single device on
pxa{27x,3xx}.
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Enhanced GPIO alternate functions descriptions,
taken from Intel PXA270 Developers Manual.
Signed-off-by: Robert Jarzmik <rjarzmik@free.fr>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Expose control of the PXA3xx 13MHz CLK_POUT pin via the clock API
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch adds the base files for the PB1176 platform support.
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This patch adds the base files for the PB11MPCore platform support.
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This patch changes the IO_ADDRESS macro for the RealView platforms to
accomodate a wider range of physical addresses on PB11MPCore.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The upcoming PB11MPCore and PB1176 have different memory maps and some
of the definitions in platform.h are no longer common. This patch
moves them to the board-eb.h file and updates their usage in
realview_eb.c.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Since the PB1176 has different UART base addresses, this patch moves
the definitions form platorm.h to board-eb.h. It also modifies
uncompress.h to detect the platform type at run-time.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This patch moves the timer definitions from platform.h into board-eb.h
as they are different on PB11MPCore and PB1176. It also adds
timerX_va_base variables in core.c which are set by the
realview_eb_timer_init function before invoking realview_timer_init.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This patch moves the patch definitions into board-eb.h and
realview_eb.c (from core.c) as they are different on the PB11MPCore
and PB1176 platforms.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This is in preparation for the RealView PB11MPCore and PB1176 patches
which have different base addresses for the GIC.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This patch moves the SCU initialisation from __v6_setup to the
smp_prepare_cpus() function as it relies on platform-specific
settings. Changes to get_core_count() are mainly for allowing cleaner
code with the upcoming PB11MPCore patches.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This patch adds a prefetch abort handler similar to the data abort one
and renames the latter for consistency. Initial implementation by Paul
Brook with some renaming by Catalin Marinas.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Juergen Beisert