In the case offset is 20 ... 23, the equation to get the register should be:
INTEL_MSIC_GPIO1HV0CTLO - offset + 20
With above equation, we can get below mapping between offset and the register:
offset is 20: INTEL_MSIC_GPIO1HV0CTLO
offset is 21: INTEL_MSIC_GPIO1HV1CTLO
offset is 22: INTEL_MSIC_GPIO1HV2CTLO
offset is 23: INTEL_MSIC_GPIO1HV3CTLO
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add gpio support for Intel MSIC chips found in Intel Medfield platforms.
MSIC supports totally 24 GPIOs with 16 low voltage and 8 high voltage pins.
Driver uses MSIC mfd interface for MSIC access.
(Updated comment to indicate why locking is actually safe)
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Axel Lin