Commit Graph

67 Commits

Author SHA1 Message Date
Paul Mundt 9d56dd3b08 sh: Mass ctrl_in/outX to __raw_read/writeX conversion.
The old ctrl in/out routines are non-portable and unsuitable for
cross-platform use. While drivers/sh has already been sanitized, there
is still quite a lot of code that is not. This converts the arch/sh/ bits
over, which permits us to flag the routines as deprecated whilst still
building with -Werror for the architecture code, and to ensure that
future users are not added.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-01-26 12:58:40 +09:00
Nicolas Palix f701b39998 sh: Replace an explicit computation by the use of the container_of macro
The macro container_of from kernel.h performs the same
pointer arithmetic operation.

The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@@
type T;
expression mptr;
expression member;
@@

- (void *)((char *)mptr - offsetof(T, member))
+ container_of(mptr, T, member)
// </smpl>

Signed-off-by: Nicolas Palix <npalix@diku.dk>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-12-09 12:36:51 +09:00
Thomas Gleixner 648f15345a sh: Fixup last users of irq_chip->typename
The typename member of struct irq_chip was kept for migration purposes
and is obsolete since more than 2 years. Fix up the leftovers.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-sh@vger.kernel.org
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-11-18 10:50:22 +09:00
Stuart Menefy 6000fc4d6f sh: Fixes some write posting issues in the interrupt handling for SH
It is possible for the CPU to re-enable it's interrupt block bit
before the write to the interrupt controller has actually masked out
the external interupt at the controller. We get around this by
reading back from the interrupt controller which will ensure the
write has happened.

Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-08-24 18:27:33 +09:00
Paul Mundt 54ff328b46 sh: Tie sparseirq in to Kconfig.
Now that the dependent patches are merged, we are ready to enable
sparseirq support. This simply adds the Kconfig option, and then converts
from the _cpu to the _node allocation routines to follow the upstream
sparseirq API changes.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-06-11 10:33:09 +03:00
Paul Mundt 3709ab8dfa sh: irq: Fix up imask build warnings.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-05-26 13:52:28 +09:00
Paul Mundt 2f3ed17e01 sh: Wrap irq_to_desc_alloc_cpu() around CONFIG_SPARSE_IRQ temporarily.
irq_to_desc_alloc_cpu() has been renamed to irq_to_desc_alloc_node() in
-next, but as we can not presently enable SPARSE_IRQ without the early
irq_desc alloc patch, protect it with an ifdef until the interface has
settled and we are ready to enable it system-wide.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-05-22 13:47:52 +09:00
Paul Mundt 05ff3004d2 sh: irq: Teach ipr and intc about dynamically allocating irq_descs.
This hooks in irq_to_desc_alloc_cpu() to the necessary code paths in the
intc and ipr controller registration paths. As these are the primary call
paths for all SH CPUs, this alone will make all CPUs sparse IRQ ready.

There is the added benefit now that each CPU contains specific IPR and
INTC tables, so only the vectors with interrupt sources backing them will
ever see an irq_desc instantiation. This effectively packs irq_desc
down to match the CPU, rather than padding NR_IRQS out to cover the valid
vector range.

Boards with extra sources will still have to fiddle with the nr_irqs
setting, but they can continue doing so through the machvec as before.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-05-22 01:28:33 +09:00
Paul Mundt fa1d43ab45 sh: irq: Convert from irq_desc[] to irq_to_desc().
This converts a few places that were using the old irq_desc[] array over
to the shiny new irq_to_desc() helper. Preperatory work for sparse irq
support.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-05-22 01:26:16 +09:00
Paul Mundt 55620c86eb sh: irq: Rework the SR.IMASK bitmap handling.
This tidies up how the SR.IMASK bitmap is managed, using the bitmap API
directly instead. At the same time, tidy up the irq_chip conversion a
bit.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-05-22 01:16:17 +09:00
Paul Mundt c51279ec0d sh: Kill off unused SH-5 irq_describe cruft.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-05-07 18:17:20 +09:00
Paul Mundt 0fb849b9d7 sh: Integrate the SH-5 onchip_remap() more coherently.
Presently this is special-cased for early initialization. While there are
situations where these static early initializations are still necessary,
with minor changes it is possible to use this for the regular ioremap
implementation as well. This allows us to kill off the special-casing for
the remap completely and to start tidying up all of the SH-5
special-casing in drivers.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-05-07 18:10:27 +09:00
Thomas Gleixner d804983982 sh: remove obsolete hw_interrupt_type
Impact: cleanup

Convert the last remaining users to struct irq_chip and remove the
define.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-05-03 17:28:13 +09:00
Paul Mundt bbfbd8b151 sh: Move the shared INTC code out to drivers/sh/
The INTC code will be re-used across different architectures, so move
this out to drivers/sh/ and include/linux/sh_intc.h respectively.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-10-01 16:13:54 +09:00
Paul Mundt 62429e0364 sh: Use __raw_xxx() I/O accessors for INTC and IPR.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-10-01 15:19:10 +09:00
roel kluin b21a910435 sh: intc_prio_data() test before subtraction on unsigned
bit is unsigned, so test before subtraction

Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-09-10 12:01:46 +09:00
Paul Mundt f15cbe6f1a sh: migrate to arch/sh/include/
This follows the sparc changes a439fe51a1.

Most of the moving about was done with Sam's directions at:

http://marc.info/?l=linux-sh&m=121724823706062&w=2

with subsequent hacking and fixups entirely my fault.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-07-29 08:09:44 +09:00
Yoshihiro Shimoda 6bdfb22a8e sh: add interrupt ack code to sh4a
This patch is based on interrupt acknowledge code for external
interrupt sources on sh3 processors and adds on sh4a processors.

Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-07-28 18:10:33 +09:00
Adrian Bunk 2beb0e2893 sh/kernel/cpu/irq/intc-sh5.c build fix
This patch fixes the following build error caused by
commit a1dc4b59fa
(sh: intc_sh5 depends on cayman board for IRQ priority table.):

<--  snip  -->

...
  CC      arch/sh/kernel/cpu/irq/intc-sh5.o
/home/bunk/linux/kernel-2.6/git/linux-2.6/arch/sh/kernel/cpu/irq/intc-sh5.c: In function 'plat_irq_setup':
/home/bunk/linux/kernel-2.6/git/linux-2.6/arch/sh/kernel/cpu/irq/intc-sh5.c:257: error: expected declaration or statement at end of input
make[4]: *** [arch/sh/kernel/cpu/irq/intc-sh5.o] Error 1

<--  snip  -->

Reported-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-06-02 12:29:07 +09:00
Magnus Damm 4370fe1c06 sh: intc register modify fix
Make sure register modifications stay atomic. Fixes processors with
shared priority register masking. Dual bitmap masking is unaffected.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-05-08 19:52:07 +09:00
Magnus Damm 720be99006 sh: no high level trigger on some sh3 cpus
The processor models sh7706, sh7707 and sh7709 don't support high
level trigger sense configuration. And the intc code looks like
crap these days so what's the difference.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-05-08 19:52:06 +09:00
Magnus Damm d58876e289 sh: add interrupt ack code to sh3
This patch adds interrupt acknowledge code for external interrupt
sources on sh3 processors. Only really required for edge triggered
interrupts, but we ack regardless of sense configuration.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-05-08 19:52:03 +09:00
Paul Mundt a1dc4b59fa sh: intc_sh5 depends on cayman board for IRQ priority table.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-05-08 19:51:43 +09:00
Paul Mundt 43081e1833 sh: Shut up some trivial build warnings.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-02-14 14:22:11 +09:00
Magnus Damm d847afe7d4 sh: remove maskreg irq code
This patch removes the maskreg irq code since it is not in use anymore.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-02-14 14:22:10 +09:00
Magnus Damm 7f3edee81f sh: intc - remove default interrupt priority tables
This patch removes interrupt priority tables from the intc code.
Optimal priority assignment varies with embedded application anyway,
so keeping the interrupt priority tables together with cpu-specific
code doesn't make sense.

The function intc_set_priority() should be used instead to set the
desired interrupt priority level.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-01-28 13:19:02 +09:00
Paul Mundt a23ba43573 sh: comment tidying for sh64->sh migration.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-01-28 13:18:58 +09:00
Paul Mundt 18bc81319b sh: Get the mach-cayman IRQ support building.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-01-28 13:18:54 +09:00
Paul Mundt cc8eae7f51 sh: imask IRQ depends on sh32.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-01-28 13:18:43 +09:00
Paul Mundt b2078fa221 sh: Kill off dead ipr_irq_demux().
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-10-31 15:17:03 +09:00
Magnus Damm f18d533e3c sh: intc - initial SMP support.
This implements initial support for the SMP INTC (particularly
INTC2) controllers.

These are largely implemented as conventional blocks, with
register sets grouped together at fixed strides relative to
the CPU id.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-21 18:16:42 +09:00
Magnus Damm 1254d1db11 sh: remove CONFIG_CPU_HAS_INTC_IRQ
All processor specific interrupt code is now converted to make use
of the new intc code. The config option CONFIG_CPU_HAS_INTC_IRQ is
because of that pointless.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-21 11:57:51 +09:00
Magnus Damm 3d37d94e5a sh: intc - primary priority masking fixes
This patch contains various intc fixes for problems reported by
Markus Brunner on the linuxsh-dev mailing list:

http://marc.info/?l=linuxsh-dev&m=118701948224991&w=1

Apart from added comments, the fixes are:

- add intc_set_priority() function prototype to hw_irq.h
- fix off-by-one error in intc_set_priority()
- make sure _INTC_WIDTH() is set for primary priority masking

Big thanks to Markus for finding these problems. Version two fixes
a compile error and an inverted primary check.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Acked-by: Markus Brunner <super.firetwister@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-21 11:57:50 +09:00
Magnus Damm 73505b445d sh: intc - rework core code
This patch reworks the intc core, implementing the following features:

- Support dual priority registers - one set and one clear register
- All 8/16/32 bit register combinations are now supported
- Both single mask and single enable bitmap register are supported
- Add code to set interrupt priority
- Speedup sense and priority configuration code
- Allocate data using bootmem, allows intc data structures to be
  __initdata
- Save memory - allocated memory footprint is smaller than intc
  structures

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-21 11:57:50 +09:00
Magnus Damm 6ef5fb2cfc sh: intc - add a clear register to struct intc_prio_reg
We need a secondary register member in struct intc_prio_reg to support
dual priority registers used by ipi on x3.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-21 11:57:49 +09:00
Paul Mundt 6d64d4256c sh: intc: Fix sense regs oops for IRL IRQs.
IRL doesn't always define sense registers, so don't bother trying to
iterate through the table. This ended up causing an oops on SH-X3
when using IRL mode.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-21 11:57:48 +09:00
Magnus Damm 96290d808f sh: remove intc2 code
There is no point in keeping around the now unused intc2 code.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-21 11:57:48 +09:00
Magnus Damm 51da64264b sh: intc - add single bitmap register support
This patch adds single bitmap register support to intc. The current
code only handles 16 and 32 bit registers where a set bit means
interrupt enabled, but this is easy to extend in the future.

The INTC_IRQ() macro is also added to provide a way to hook in
interrupt controllers for FPGAs in boards or companion chips.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-21 11:57:47 +09:00
Magnus Damm d89ddd1c84 sh: remove support for sh7300 and solution engine 7300
This patch removes old dead code:
- kill off sh7300 cpu support
- get rid of broken solution engine 7300 board support

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-07-26 15:37:57 +09:00
Magnus Damm 347b9bdddb sh: remove old broken pint code
The code in arch/sh/kernel/cpu/irq/pint.c doesn't compile, so let's
get rid of it to make space for a future pint implementation on top
of intc.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-07-25 10:46:32 +09:00
Magnus Damm 680c45981a sh: intc - improve group support
This patch improves intc group support, ie it makes it possible to
group interrupts together and mask / unmask the entire group. This
also works with priorities, so setting a priority for an entire group
is also possible. This patch is needed to properly support certain
processors such as the 7780.

Fixes for NULL pointers in DECLARE_INTC_DESC() are also included.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-07-20 12:18:21 +09:00
Magnus Damm 02ab3f7079 sh: intc - shared IPR and INTC2 controller
This is the second version of the shared interrupt controller patch
for the sh architecture, fixing up handling of intc_reg_fns[].

The three main advantages with this controller over the existing
ones are:

	- Both priority (ipr) and bitmap (intc2) registers are
	  supported
	- External pin sense configuration is supported, ie edge
	  vs level triggered
	- CPU/Board specific code maps 1:1 with datasheet for
	  easy verification

This controller can easily coexist with the current IPR and INTC2
controllers, but the idea is that CPUs/Boards should be moved over
to this controller over time so we have a single code base to
maintain.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-07-20 12:18:20 +09:00
Paul Mundt 027e56e685 sh: Hook up hard_smp_processor_id() for INTC2 block.
We need to know the CPU ID in order to calculate the mask and ack
registers effectively. Stub this in for UP.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-06-20 18:23:49 +09:00
Magnus Damm 68abdbbb03 sh: rework ipr code
This patch reworks the ipr code by grouping the offset array together
with the ipr_data structure in a new data structure called ipr_desc.
This new structure also contains the name of the controller in struct
irq_chip. The idea behind putting struct irq_chip in there is that we
can use offsetof() to locate the base addresses in the irq_chip
callbacks. This strategy has much in common with the recently merged
intc2 code.

One logic change has been made - the original ipr code enabled the
interrupts by default but with this patch they are all disabled by
default.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-06-15 18:56:19 +09:00
Magnus Damm d619500aed sh: rework intc2 code
The shared intc2 code currently contains cpu-specific #ifdefs.
This is a tad unclean and it prevents us from using the shared code
to drive board-specific irqs on the se7780 board.

This patch reworks the intc2 code by moving the base addresses of
the intc2 registers into struct intc2_desc. This new structure also
contains the name of the controller in struct irq_chip. The idea
behind putting struct irq_chip in there is that we can use offsetof()
to locate the base addresses in the irq_chip callbacks.

One logic change has been made - the original shared intc2 code
enabled the interrupts by default but with this patch they are all
disabled by default.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-06-15 10:41:54 +09:00
Simon Arlott e868d61272 spelling fixes: arch/sh/
Spelling fixes in arch/sh/.

Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-05-21 14:31:39 +09:00
Nobuhiro Iwamatsu 2a8ff4596c sh: Solution Engine SH7705 board and CPU updates.
This fixes up SH7705 CPU support and the SE7705 board
for some of the recent changes.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.zh@hitachi.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-05-07 02:11:56 +00:00
Paul Mundt 32351a28a7 sh: Add SH7785 Highlander board support (R7785RP).
This adds preliminary support for the SH7785-based Highlander board.
Some of the Highlander support code is reordered so that most of it
can be reused directly.

This also plugs in missing SH7785 checks in the places that need it,
as this is the first board to support the CPU.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-05-07 02:10:53 +00:00
Takashi YOSHII f725b5ee1e sh: shmin updates.
This fixes up shmin (and SH7706/SH7708) IPR support for some of the
recent API changes.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-02-13 10:54:44 +09:00
Jamie Lenehan ea0f8feaa0 sh: sh775x/titan fixes for irq header changes.
The following moves the creation of IPR interupts into setup-7750.c
and updates a few other things to make it all work after the "Drop
CPU subtype IRQ headers" commit. It boots and runs fine on my titan
board.

 - adds an ipr_idx to the ipr_data and uses a function in the subtype
   code to calculate the address of the IPR registers

 - adds a function to enable individual interrupt mode for externals
   in the subtype code and calls that from the titan board code
   instead of doing it directly.

 - I changed the shift in the ipr_data to be the actual # of bits to
   shift, instead of the numnber / 4 - made it easier to match with
   the manual.

Signed-off-by: Jamie Lenehan <lenehan@twibble.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2006-12-06 12:05:02 +09:00