Commit Graph

18 Commits

Author SHA1 Message Date
Russell King bbba756069 Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into devel-stable 2011-01-15 13:24:02 +00:00
Kukjin Kim 8267e2e0fb Merge branch 'dev/s5pv310-cpufreq' into next-s5pv310 2011-01-03 18:58:50 +09:00
Kukjin Kim fa353e9f40 Merge branch 'dev/s5pv310-irq' into next-s5pv310 2010-12-31 08:01:08 +09:00
Changhwan Youn d6d8b48199 ARM: S5PV310: Add support Power Domain
This patch adds support Power Domain for S5PV310 and S5PC210.

Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-12-30 09:37:02 +09:00
Changhwan Youn a50eb1c768 ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register
This patch is applied according to the commit 1a8e41cd67
(ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register).

Actually, S5PV310 has same cache controller(PL310).

Following is from Catalin Marinas' commit.

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Cc: <stable@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-12-30 09:37:02 +09:00
Sunyoung Kang dd0b7e20da ARM: S5PV310: Add DMC registers and map_desc
This patch adds DMC io mapping for access it and adds registers.
This is used in checking DRAM memory type.

Signed-off-by: Sunyoung Kang <sy0816.kang@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-12-23 14:53:39 +09:00
Russell King ff2e27ae0b ARM: GIC: consolidate gic_cpu_base_addr to common GIC code
Every architecture using the GIC has a gic_cpu_base_addr pointer for
GIC 0 for their entry assembly code to use to decode the cause of the
current interrupt.  Move this into the common GIC code.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-14 19:21:42 +00:00
Russell King b580b899dd ARM: GIC: provide a single initialization function for boot CPU
Provide gic_init() which initializes the GIC distributor and current
CPU's GIC interface for the boot (or single) CPU.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-14 19:21:30 +00:00
Changhwan Youn 1f2d6c49f0 ARM: S5PV310: Limit the irqs which support cascade interrupt
The irqs from SPI(0) to SPI(39) and SPI(51), SPI(53) are connected to the
interrupt combiner. This patch limits the irqs which should be initialized
to support cascade interrupt.

Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-12-08 18:11:37 +09:00
Daein Moon 09596ba07e ARM: S5PV310: Add support SROMC
This patch adds support SROMC for S5PV310 and S5PC210.

Signed-off-by: Daein Moon <moon9124@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-10-26 08:40:12 +09:00
Kyungmin Park 1cf0eb7997 ARM: S5PV310: Add L2 cache init function in cpu.c
This patch adds L2 cache initialization code in cpu.c of ARCH_S5PV310.
It includes TAG and Data latency, Prefetch, and Power configurations.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-10-25 16:11:16 +09:00
Jongpill Lee 37ea63b14b ARM: S5P: Add initial map for GPIO2 and GPIO3
This patch adds initial map for GPIO2 and GPIO3.
S5PV310/S5PC210 has separated GPIO1, GPIO2 and GPIO3.

Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-10-25 16:06:22 +09:00
Hyuk Lee 1036c3ab60 ARM: S5PV310: Add HSMMC platform data
This patch adds initialization HSMMC device information.
And HSMMC platform data like card detect, data bus width
and capability is configured.

Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-10-25 16:02:26 +09:00
Kukjin Kim fe0cdec8ba ARM: S5PV310: Fix build error on GPIO map
This patch fixes build error about GPIO address due to
conflict of commit 4d914705 and 19a2c065.

- commit 4d914705: Fix on GPIO base addresses
- commit 19a2c065: Moves initial map for merging S5P64X0

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-10-19 08:02:57 +09:00
Kukjin Kim 19a2c06548 ARM: S5P: Moves initial map for merging S5P64X0
This patch moves some initial maps from plat-s5p to machine,
so that can merge mach-s5p6440 and mach-s5p6450.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-10-18 10:33:34 +09:00
Changhwan Youn 766211e748 ARM: S5PV310: Fix on Secondary CPU startup
Following occurs on boot message without this patch.
    CPU1: processor failed to boot
    Brought up 1 CPUs
    SMP: Total of 1 processors activated...

This patch adds SYSRAM mapping for fixing Secondary CPU startup.
    CPU1: Booted secondary processor
    Brought up 2 CPUs
    SMP: Total of 2 processors activated...

Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-08-27 18:29:58 +09:00
Kukjin Kim c598c47d85 ARM: S5PV310: Add CMU block for S5PV310 Clock
This patch adds CMU block for S5PV310/S5PC210 clock.
(CMU: Clock Management Unit)
Of course, changed current clock addresses for it together.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-08-27 18:04:37 +09:00
Changhwan Youn 2b12b5c4ff ARM: S5PV310: Add new CPU initialization support
This patch adds Samsung S5PV310/S5PC210 CPU support.
The S5PV310/S5PC210 integrates a ARM Cortex A9 multi-core.

Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Jiseong Oh <jiseong.oh@samsung.com>
[kgene.kim@samsung.com: fix build errors]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-08-05 18:32:41 +09:00